This invention generally relates to the manufacture of devices employing wet etching processes. More specifically, this invention relates to: a method and apparatus for removing and reducing contaminants present in, or introduced during, the wet etching process, wherein the devices produced by such processes are produced without a substantial decrease in performance of the resulting device.
The continued decrease in the sizes of devices being produced from silicon or other substrate wafers in wet etching processes has made the wafers more vulnerable to contamination from particles and debris. Semiconductor manufactures utilize a number of cleaning procedures throughout the process of wafer manufacture to remove undesirable debris from the wafer surface.
Loss analysis studies have indicated that a significant source of debris that leads to a reduction in wafer yield is the presence of undesirable substances on the wafer backside and on the outer several millimeters of the feature, active or top side or surface of the wafer. These debris may comprise both contamination from foreign particles and desired and/or undesired materials and/or layers which are present in, or introduced during, the wafer manufacturing process. In one instance, desired materials may be deposited or collected at or near this edge of the wafer without the benefit of tight control due to the location at the edge of the wafer. An etching process that removes all materials on the wafer backside and on the feature side along the edge of the wafer without adversely impacting the ultimate performance of the devices being produced will generally remove the source of contamination, and thus increase wafer yield.
These materials may be removed from the backside and outer feature side edges through the application of a barrier layer, followed by a thin layer of copper applied by a physical vapor deposition (PVD) process, followed by a thicker layer of copper using electroplating. However, poor quality at the edge of the wafer may result in the thin layer of copper flaking off causing contamination in subsequent steps of the etching process, or diffusing into the silicon or substrate material due to problems with the barrier layer of the substrate. Thus, the need exists for a process and apparatus to enable excess copper, and other undesirable deposits on the surface of the wafer, to be removed during the etching process.
This problem may be solved by etching away the copper layer, or other undesirable contaminants, at the edge of the wafer to a distance where all the layers being deposited on the surface of the wafer are applied to the wafer properly without adversely impacting the performance of the device produced by the etching process.
Layers that often need to be removed from the edge or other areas of the wafer are: copper, aluminum, silicon-oxide and silicon-nitrite, although it may be desirable to remove other materials from the wafer. The distance from the edge should be precisely controlled to insure that the defective areas are substantially completely removed and that there is no substantial undesired etching in the active areas of the device produced from the wafer being etched.
In one embodiment, this invention generally comprises a method and apparatus for removing unwanted material from the edge and bevel areas of a wafer, by:
Understanding of the present invention will be facilitated by consideration of the following detailed description of the embodiments of the present invention taken in conjunction with the accompanying drawings, in which like numerals refer to like parts, and wherein:
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purposes of clarity, many other elements which may be found in the present invention. Those of ordinary skill in the pertinent art will recognize that other elements are desirable and/or required in order to implement the present invention. However, because such elements are well known in the art, and because such elements do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein.
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Wafer 10 is processed feature side 401 down on a rotating chuck 20. Wafer 10 floats on nitrogen or other gas cushion 303 that prevents contact with chuck 20 and prevents chemical etching fluid or other chemistry from reaching active area 401 of wafer 10. Chuck 20 contains bevel flow ring 307 that can be set to a fixed gap 305 between flow ring 307 and wafer 10. Chemical etching fluid or other chemistry is dispensed from above on the backside or non-active area 404 of wafer 10. Due to the centrifugal force, the chemistry flows to the outer edge of wafer 10. The chemistry then flows off wafer 10 edge and down onto flow ring 307. The chemistry fills bevel flow ring 307 and contacts the outer edge (typically by about several millimeters) on feature side 401 of wafer 10. With a relatively slow rotational velocity (typically between about 50 rpm and about 1200 rpm), chemistry is held by surface tension in gap 305 between wafer 10 and flow ring 307. The etch distance from the edge of wafer 10 is determined by the distance that flow ring 307 overlaps with wafer 10. The fluid in gap 305 also acts as a seal and prevents fluid from splashing onto active area 401 of wafer 10.
Once the etching process is complete, the rotational velocity is increased (typically from between about 500 rpm to about 2000 rpm) to force the chemistry out of gap 305.
If multiple layers are present, several chemistries may be required to etch down to the desired surfaces of wafer 10. When the etching process is complete, wafer 10 may be rinsed and spun dry.
In the instant embodiment, gap 305 varies between about 0.001″ and about 0.015″ depending on the viscosity and surface tension of the etching fluid. Also in this embodiment, wafer 10 and flow ring 307 may overlap by about 0.5 to about 5 mm which determines the distance from the edge of the etched area of wafer 10.
The disclosure herein is directed to certain features of the elements and methods of the invention disclosed as well as others that will be apparent to those skilled in the art in light of the disclosure herein. Thus, it is intended that the present invention covers all such modifications and variations of this invention, provided that those modifications come within the scope of the claims granted herein and the equivalents thereof.
This application claims priority to U.S. provisional patent application Ser. No. 60/633,061, filed Dec. 3, 2004.
Number | Date | Country | |
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60633061 | Dec 2004 | US |