The invention relates generally to field effect transistors and in particular to wide bandgap semiconductor based field effect transistors.
Electronic devices based on wide bandgap semiconductors offer superior high voltage, high power, high temperature, and high frequency operation. A number of power devices use the wide bandgap, high power and harsh environment tolerance of gallium nitride (GaN). Heterostructures based on aluminum gallium nitride (AlGaN) and GaN provide a great deal of flexibility for novel device design and are used for many power device applications.
Most GaN based devices are grown heteroepitaxially on foreign substrates such as sapphire and silicon carbide (SiC). Mismatches in lattice constants and thermal expansion coefficients between the epilayers and the substrates manifest as a high density of threading dislocations and a large residual strain, which may be detrimental to the performance of high power electronic devices.
A field effect transistor (FET) includes a drain, a source, and a gate. The gate is separated from the source and drain by a dielectric layer. On application of a voltage or an electric field on the gate, the source to drain current may be controlled. High temperature application of a FET may result in dielectric breakdown at the dielectric/semiconductor interface resulting in gate leakage currents that may adversely affect the performance of the FET. Another limitation in high power applications sometimes results from ohmic structures such as metal/semiconductor junctions. At high temperatures, device performance may not be reproducible due to inconsistency in the behavior of the metal/semiconductor junctions.
Therefore, there is a need to address these issues to enhance the performance of field effect transistors. It would be desirable to provide new structures and methods related to fabrication of wide bandgap semiconductor based field effect transistors.
In accordance with one embodiment of the invention, a wide bandgap semiconductor based field effect transistor (FET) is provided. The FET includes a source region, a drain region, and an intermediate region situated between the source region and the drain region. The intermediate region forms a gate channel of the FET on application of a stimulus to the intermediate region.
In another embodiment of the invention, a FET with a GaN substrate is provided. The FET includes a source region, a drain region, and an intermediate region situated between the source region and the drain region. The intermediate region forms a gate channel of the FET on application of a stimulus to the intermediate region.
In yet another embodiment of the invention, a FET with a GaN substrate is provided. The FET includes a source region, a drain region, and an intermediate region situated between the source region and the drain region. The intermediate region includes a graded layer that transitions from GaN towards AlGaN or aluminum nitride at a top surface of the graded layer.
These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
In accordance with an embodiment of the invention, a wide bandgap semiconductor based field effect transistor (FET) is provided. The FET includes a source region, a drain region, and an intermediate region situated between the source region and the drain region. A gate channel forms on the intermediate region of the FET on application of a stimulus to the intermediate region.
A source region 108 and a drain region 110 are patterned within the substrate 102. In the illustrated embodiment, the source region 108 and the drain region 110 are in contact with the top surface 104. The source region 108 and the drain region 110 are n doped, and the concentration of n doping, in this example, is in a range from about 1017 cm−3 to about 1018 cm−3.
The region between the source region 108 and the drain region 110 is marked as intermediate region 112. In the illustrated example, the intermediate region 112 is in contact with the top surface 104 of the GaN substrate 102.
A source contact 114 and a drain contact 116 are provided on the source region 108 and the drain region 110 respectively. In one embodiment, the source contact 114 and the drain contact 116 are made of metals such as platinum, nickel, silver, or gold, for example.
GaN, being polar, lacks inversion symmetry and exhibits spontaneous polarization that manifests itself as a polarization charge. Due to the polarization charge, a spontaneous electric field is formed which results in an increased sheet carrier charge density. The polarization charge may be further induced by application of stimulus. The further induced polarization is referred to herein as piezoelectric polarization. The total polarization on GaN is a sum of spontaneous polarization and piezoelectric polarization. Embodiments of the present invention make use of the piezoelectric polarization to form a field effect transistor, and use the total polarization to maximize the flow of charge from a source to drain of the FET. Although polarization is expected to be highest for GaN, polarization also occurs in other wide bandgap materials such as SiC and AlN.
On application of a stimulus on the intermediate region 112, polarization charge builds up on the intermediate region 112 to form a channel layer 118 with high charge density. The polarization charge build-up and the resultant flow of charge or current from source region 108 to drain region 110 may be varied by controlling the stimulus.
The current from source region to drain region is a function of the stimulus on the intermediate region. This is similar in behavior to a conventional FET, wherein on applying a bias across the gate, the source to drain current may be controlled. The channel layer is otherwise termed as a gate channel since it performs the function of a gate channel of a conventional FET.
As compared to a conventional FET, the FET illustrated in
The current across the source to drain is measured in terms of conductance which is a function of concentration and mobility of charge carriers of the gate channel. The conductance depends on the amount of stimulus and also on the distance between the source region and the drain region. The distance between the source region and the drain region may be adjusted to maximize conductance. The source region 108 and the drain region 110 are typically separated by a distance ranging from about 0.5 microns to about 2 microns. In a more specific embodiment, the distance between the source region and the drain region is in a range from about 1 micron to about 1.5 microns. In a still more specific embodiment, the distance between the source region and the drain region is about 1 micron.
In
The area between the source region 206 and the drain region 208, as shown in the illustrated example, is denoted as intermediate region 216. A graded layer 218 is epitaxially grown over the GaN substrate 202 and forms part of the intermediate region 216. The graded layer transitions from GaN at a bottom surface 220 of the graded layer to AlGaN or AlN at the top surface 222 of the graded layer. The amount of aluminum in the AlGaN may be varied to obtain the graded layer. In one example, AlGaN having a formula of Alx Ga1−xN, the (x) may take a value from about 0 at the GaN substrate to about 1 at the top surface of the graded layer. In certain embodiments, the graded layer includes a layered structure with a number of layers of differing aluminum concentration. In such embodiments, the topmost layer at the top surface of the graded layer in one example is AlN.
The lattice constant of the AlGaN is about 3.110 Å while the lattice constant of GaN is about 3.189 Å. The difference in the lattice constants between the two is about 2.4% and results in a strain at the interface between the GaN substrate and the graded layer 218. A stimulus on the GaN induces piezoelectric polarization below an interface between the GaN/AlGaN in addition to the inherent spontaneous polarization of GaN and AlGaN, as mentioned earlier.
Upon applying a stimulus on the intermediate region, a gate channel 224 is formed. In the illustrated example, the gate channel 224 forms in the intermediate region 216, below an interface between the GaN substrate and the graded layer. The graded layer shifts the sheet carrier charge density from the top surface 222 to the region below the interface of the intermediate region and the graded layer.
The thickness of the gate channel may be controlled by varying the concentration of aluminum in the AlGaN. In the shown example, thickness of the gate channel is about 500 Å. In certain embodiments, thickness of the gate channel is greater than about 500 Å.
The FETs as described above are operable at high temperature due to the presence of wide bandgap semiconductor and also due to the absence of gate metal contacts. In one example, the FET is operable at temperatures in excess of 200 degree Celsius. In certain embodiments, the operating temperature is about 700 degree Celsius.
A graded layer 218 is epitaxially grown in the trough 203 of the GaN substrate 202, as shown in
Non-limiting examples of stimulus includes pressure, strain, and combinations of pressure and strain. In one embodiment as shown in
As shown at the bottom of
The FETs that are described herein are operable either as traditional FETs or as pressure or strain sensors. Because the source to drain current is a function of the stimulus applied this may be utilized to build a strain or pressure sensor. In one embodiment, the conductance between the source and the drain region is used to measure the strain or pressure applied on the GaN substrate.
While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.