Claims
- 1. A method of managing memory, comprising:
examining current and future instructions operating on a stack; determining stack trend information; and utilizing the trend information to reduce data traffic between various levels of a memory.
- 2. The method of claim 1, wherein determining the trend information includes examining future instructions to determine if the size of the stack is going to decrease as a result of future instructions.
- 3. The method of claim 2, wherein a predetermined number of instructions are used in determining stack trend information.
- 4. The method of claim 3, wherein the number of predetermined instructions is at least two.
- 5. The method of claim 3, wherein the cache memory maintains a single dirty cache line for stack data.
- 6. The method of claim 3, wherein if a dirty cache line needs to be written back, then analyzing the trend information, which includes determining which word of the dirty cache line is going to be written to.
- 7. The method of claim 1, wherein the levels of memory comprise a cache memory containing multiple cache lines and a main memory, and wherein the trend information is used to restrict writing dirty cache lines from cache memory to main memory when the trend information indicates the stack is decreasing.
- 8. The method of claim 1, wherein determining the trend information includes examining future instructions to determine if the size of the stack is going to increase as a result of future instructions.
- 9. The method of claim 8, wherein determining if a line is written back includes analyzing the trend information and includes examining a dirty cache line to determine which word of the dirty cache line is going to be written to.
- 10. The method of claim 9, wherein the dirty cache line is written from a cache memory to a main memory.
- 11. A computer system, comprising:
a processor; a memory coupled to the processor; a stack that exists in memory and contains stack data; a memory controller coupled to the memory; trend logic; wherein the processor executes instructions; wherein the trend logic provides trend information about the stack to the controller; and wherein the trend information about the stack is based on at least one future instruction.
- 12. The computer system of claim 11, further comprising an instruction decoder comprising a first portion that decodes current instructions and a second portion that decodes future instructions.
- 13. The computer system of claim 12, wherein the trend logic determines a net stack trend based on current instruction and future instruction information coming from the decode logic.
- 14. The computer system of claim 12, wherein the second potion of the decoder is adjusted so that the number of future instructions that are decoded equals at least two.
- 15. The computer system of claim 11, wherein the memory further includes a cache memory containing multiple cache lines and a main memory, and wherein the trend information is used to restrict writing dirty cache lines from cache memory to main memory when the trend information indicates the stack is decreasing.
- 16. The computer system of claim 11, wherein the memory further includes a cache memory and a main memory, and wherein the cache memory contains a dirty cache line, and wherein the dirty cache line is written to main memory if the trend information indicates the stack is increasing.
- 17. A method, comprising:
issuing a write request to a cache memory, wherein the cache memory includes multiple cache lines; determining whether the write request refers to a predetermined word within a dirty cache line; and determining whether the size of a stack is increasing or decreasing.
- 18. The method of claim 17, further comprising determining whether the write request will be to the end of a dirty cache line.
- 19. The method of claim 18, wherein the stack size is increasing and the dirty cache line is written to a main memory.
- 20. The method of claim 18, wherein the stack size decreasing and the dirty cache line is retained in the cache memory.
Priority Claims (1)
Number |
Date |
Country |
Kind |
03291914.4 |
Jul 2003 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Application Serial No. 60/400,391 titled “JSM Protection,” filed Jul. 31, 2002, incorporated herein by reference. This application also claims priority to EPO Application No. 03291914.4, filed Jul. 30, 2003 and entitled “Write Back Policy For Memory,” incorporated herein by reference. This application also may contain subject matter that may relate to the following commonly assigned co-pending applications incorporated herein by reference: “System And Method To Automatically Stack And Unstack Java Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35422 (1962-05401); “Memory Management Of Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35423 (1962-05402); “Memory Management Of Local Variables Upon A Change Of Context,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35424 (1962-05403); “A Processor With A Split Stack,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35425 (1962-05404); “Using IMPDEP2 For System Commands Related To Java Accelerator Hardware,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35426 (1962-05405); “Test With Immediate And Skip Processor Instruction,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35427 (1962-05406); “Test And Skip Processor Instruction Having At Least One Register Operand,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35248 (1962-05407); “Synchronizing Stack Storage,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35429 (1962-05408); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35430 (1962-05409); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35432 (1962-05411); “Mixed Stack-Based RISC Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35433 (1962-05412); “Processor That Accommodates Multiple Instruction Sets And Multiple Decode Modes,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35434 (1962-05413); “System To Dispatch Several Instructions On Available Hardware Resources,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35444 (1962-05414); “Micro-Sequence Execution In A Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35445 (1962-05415); “Program Counter Adjustment Based On The Detection Of An Instruction Prefix,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35452 (1962-05416); “Reformat Logic To Translate Between A Virtual Address And A Compressed Physical Address,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35460 (1962-05417); “Synchronization Of Processor States,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35461 (1962-05418); “Conditional Garbage Based On Monitoring To Improve Real Time Performance,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35485 (1962-05419); “Inter-Processor Control,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35486 (1962-05420); “Cache Coherency In A Multi-Processor System,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35637 (1962-05421); “Concurrent Task Execution In A Multi-Processor, Single Operating System Environment,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35638 (1962-05422); and “A Multi-Processor Computing System Having A Java Stack Machine And A RISC-Based Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35710 (1962-05423).
Provisional Applications (1)
|
Number |
Date |
Country |
|
60400391 |
Jul 2002 |
US |