Alan Louis Herrmann

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for placing and routing partial reconfiguratio...
- Patent number 10,242,146
- Issue date Mar 26, 2019
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placing and routing partial reconfiguratio...
- Patent number 9,361,421
- Issue date Jun 7, 2016
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial reconfiguration and in-system debugging
- Patent number 9,041,431
- Issue date May 26, 2015
- Altera Corporation
- Alan Louis Herrmann
- G01 - MEASURING TESTING
Information Patent Grant
Partial reconfiguration and in-system debugging
- Patent number 8,686,753
- Issue date Apr 1, 2014
- Altera Corporation
- Alan Louis Herrmann
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for placement and routing of partial reconfigu...
- Patent number 8,671,377
- Issue date Mar 11, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLD debugging hub
- Patent number 7,036,046
- Issue date Apr 25, 2006
- Altera Corporation
- Nicholas James Rally
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced embedded logic analyzer
- Patent number 6,704,889
- Issue date Mar 9, 2004
- Altera Corporation
- Kerry Veenstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration memory integrated circuit
- Patent number 6,614,259
- Issue date Sep 2, 2003
- Altera Corporation
- Chris Couts-Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced embedded logic analyzer
- Patent number 6,460,148
- Issue date Oct 1, 2002
- Altera Corporation
- Kerry Veenstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for in-system programming of integrated circui...
- Patent number 6,408,432
- Issue date Jun 18, 2002
- Altera Corporation
- Alan L. Herrmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded logic analyzer for a programmable logic device
- Patent number 6,389,558
- Issue date May 14, 2002
- Altera Corporation
- Alan L. Herrmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced embedded logic analyzer
- Patent number 6,286,114
- Issue date Sep 4, 2001
- Altera Corporation
- Kerry Veenstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration memory integrated circuit
- Patent number 6,259,271
- Issue date Jul 10, 2001
- Altera Corporation
- Chris Couts-Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced embedded logic analyzer
- Patent number 6,247,147
- Issue date Jun 12, 2001
- Altera Corporation
- Kerry Beenstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded logic analyzer for a programmable logic device
- Patent number 6,182,247
- Issue date Jan 30, 2001
- Altera Corporation
- Alan L. Herrmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for in-system programming of integrated circui...
- Patent number 6,134,707
- Issue date Oct 17, 2000
- Altera Corporation
- Alan L. Herrmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration memory integrated circuit
- Patent number 6,097,211
- Issue date Aug 1, 2000
- Altera Corporation
- Chris Couts-Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration memory integrated circuit
- Patent number 6,031,391
- Issue date Feb 29, 2000
- Altera Corporation
- Chris Couts-Martin
- G11 - INFORMATION STORAGE
Information Patent Grant
Local compilation in context within a design hierarchy
- Patent number 6,026,226
- Issue date Feb 15, 2000
- Altera Corporation
- Francis B. Heile
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for programming programmable elements in programmable devices
- Patent number 5,200,920
- Issue date Apr 6, 1993
- Altera Corporation
- Kevin A. Norman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Placing and Routing Partial Reconfiguratio...
- Publication number 20160267212
- Publication date Sep 15, 2016
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placing and Routing Partial Reconfiguratio...
- Publication number 20140237441
- Publication date Aug 21, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placement and Routing of Partial Reconfigu...
- Publication number 20120227026
- Publication date Sep 6, 2012
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD debugging HUB
- Publication number 20040098638
- Publication date May 20, 2004
- Altera Corporation
- Nicholas James Rally
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced embedded logic analyzer
- Publication number 20020194543
- Publication date Dec 19, 2002
- Altera Corporation, a Delaware Corporation
- Kerry Veenstra
- G01 - MEASURING TESTING
Information Patent Application
Configuration memory integrated circuit
- Publication number 20010056558
- Publication date Dec 27, 2001
- Chris Couts-Martin
- G11 - INFORMATION STORAGE
Information Patent Application
Enhanced embedded logic analyzer
- Publication number 20010037477
- Publication date Nov 1, 2001
- Kerry Veenstra
- G01 - MEASURING TESTING

Alan Louis Herrmann

Person

Patents Grantslast 30 patents

Method and apparatus for placing and routing partial reconfiguratio...

Method and apparatus for placing and routing partial reconfiguratio...

Partial reconfiguration and in-system debugging

Partial reconfiguration and in-system debugging

Method and apparatus for placement and routing of partial reconfigu...

PLD debugging hub

Enhanced embedded logic analyzer

Configuration memory integrated circuit

Enhanced embedded logic analyzer

Apparatus and method for in-system programming of integrated circui...

Embedded logic analyzer for a programmable logic device

Enhanced embedded logic analyzer

Configuration memory integrated circuit

Enhanced embedded logic analyzer

Embedded logic analyzer for a programmable logic device

Apparatus and method for in-system programming of integrated circui...

Configuration memory integrated circuit

Configuration memory integrated circuit

Local compilation in context within a design hierarchy

Method for programming programmable elements in programmable devices

Patents Applicationslast 30 patents

Method and Apparatus for Placing and Routing Partial Reconfiguratio...

Method and Apparatus for Placing and Routing Partial Reconfiguratio...

Method and Apparatus for Placement and Routing of Partial Reconfigu...

PLD debugging HUB

Enhanced embedded logic analyzer

Configuration memory integrated circuit

Enhanced embedded logic analyzer