Alec J. Morton

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing an interconnect
- Patent number 7,541,275
- Issue date Jun 2, 2009
- Texas Instruments Incorporated
- Betty Shu Mercer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded EEPROM array techniques for higher density
- Patent number 7,471,570
- Issue date Dec 30, 2008
- Texas Instruments Incorporated
- Alec James Morton
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and devices for optimized digital and analog CMOS transisto...
- Patent number 6,680,226
- Issue date Jan 20, 2004
- Texas Instruments Incorporated
- Taylor R. Efland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Measuring integrated circuit layout efficiency
- Patent number 6,591,409
- Issue date Jul 8, 2003
- Texas Instruments Incorporated
- Ganesh Kamath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Higher voltage transistors for sub micron CMOS processes
- Patent number 6,548,874
- Issue date Apr 15, 2003
- Texas Instruments Incorporated
- Alec Morton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and devices for optimized digital and analog CMOS transisto...
- Patent number 6,468,849
- Issue date Oct 22, 2002
- Texas Instruments Incorporated
- Taylor R. Efland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECT...
- Patent number 6,413,824
- Issue date Jul 2, 2002
- Texas Instruments Incorporated
- Amitava Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated bipolar junction transistor for mixed signal circuits
- Patent number 6,303,420
- Issue date Oct 16, 2001
- Texas Instruments Incorporated
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for current ballasting and busing over active device area us...
- Patent number 5,801,091
- Issue date Sep 1, 1998
- Texas Instruments Incorporated
- Taylor R. Efland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having current ballasting and busing over active area using...
- Patent number 5,665,991
- Issue date Sep 9, 1997
- Texas Instruments Incorporated
- Taylor R. Efland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Linear predictive coding technique with one multiplication step per...
- Patent number 4,796,216
- Issue date Jan 3, 1989
- Texas Instruments Incorporated
- Karl H. Renner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital lattice filter with multiplexed fast adder/full adder for p...
- Patent number 4,740,906
- Issue date Apr 26, 1988
- Texas Instruments Incorporated
- Karl H. Renner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital lattice filter with multiplexed full adder
- Patent number 4,700,323
- Issue date Oct 13, 1987
- Texas Instruments Incorporated
- Karl H. Renner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear predictive coding technique with interleaved sequence digita...
- Patent number 4,695,970
- Issue date Sep 22, 1987
- Texas Instruments Incorporated
- Karl H. Renner
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Linear predictive coding technique with symmetrical calculation of...
- Patent number 4,686,644
- Issue date Aug 11, 1987
- Texas Instruments Incorporated
- Karl H. Renner
- G10 - MUSICAL INSTRUMENTS ACOUSTICS

Patents Applicationslast 30 patents

Information Patent Application
Embedded EEPROM array techniques for higher density
- Publication number 20070064494
- Publication date Mar 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Alec James Morton
- G11 - INFORMATION STORAGE
Information Patent Application
Interconnect and a method of manufacture therefor
- Publication number 20050239277
- Publication date Oct 27, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Betty Shu Mercer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM and flash EEPROM
- Publication number 20050145922
- Publication date Jul 7, 2005
- Joseph Farley
- G11 - INFORMATION STORAGE
Information Patent Application
Small viatops for thick copper connectors
- Publication number 20050127516
- Publication date Jun 16, 2005
- Betty Shu Mercer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Higher voltage transistors for sub micron CMOS processes
- Publication number 20030127694
- Publication date Jul 10, 2003
- Alec Morton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and devices for optimized digital and analog CMOS transisto...
- Publication number 20030032231
- Publication date Feb 13, 2003
- Taylor R. Efland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Measuring integrated circuit layout efficiency
- Publication number 20020066064
- Publication date May 30, 2002
- Ganesh Kamath
- G06 - COMPUTING CALCULATING COUNTING

Alec J. Morton

Person

Patents Grantslast 30 patents

Method for manufacturing an interconnect

Embedded EEPROM array techniques for higher density

Methods and devices for optimized digital and analog CMOS transisto...

Measuring integrated circuit layout efficiency

Higher voltage transistors for sub micron CMOS processes

Methods and devices for optimized digital and analog CMOS transisto...

METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECT...

Integrated bipolar junction transistor for mixed signal circuits

Method for current ballasting and busing over active device area us...

Device having current ballasting and busing over active area using...

Linear predictive coding technique with one multiplication step per...

Digital lattice filter with multiplexed fast adder/full adder for p...

Digital lattice filter with multiplexed full adder

Linear predictive coding technique with interleaved sequence digita...

Linear predictive coding technique with symmetrical calculation of...

Patents Applicationslast 30 patents

Embedded EEPROM array techniques for higher density

Interconnect and a method of manufacture therefor

EEPROM and flash EEPROM

Small viatops for thick copper connectors

Higher voltage transistors for sub micron CMOS processes

Methods and devices for optimized digital and analog CMOS transisto...

Measuring integrated circuit layout efficiency