Alexander E. Andreev

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Variable node processing unit
- Patent number 9,239,704
- Issue date Jan 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architectural floorplan for a structured ASIC manufactured on a 28...
- Patent number 9,024,657
- Issue date May 5, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via-configurable high-performance logic block involving transistor...
- Patent number 8,957,398
- Issue date Feb 17, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for assigning code blocks to constituent decoder...
- Patent number 8,769,372
- Issue date Jul 1, 2014
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via-configurable high-performance logic block architecture
- Patent number 8,735,857
- Issue date May 27, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Microcontroller controlled or direct mode controlled network-fabric...
- Patent number 8,677,306
- Issue date Mar 18, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock network fishbone architecture for a structured ASIC manufactu...
- Patent number 8,629,548
- Issue date Jan 14, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for using the universal multipole for the impleme...
- Patent number 8,527,851
- Issue date Sep 3, 2013
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable node processing unit
- Patent number 8,443,033
- Issue date May 14, 2013
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for implementing parity computation in a parallel architec...
- Patent number 8,347,167
- Issue date Jan 1, 2013
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scheme for erasure locator polynomial calculation in error-and-eras...
- Patent number 8,286,060
- Issue date Oct 9, 2012
- LSI Corporation
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cryptographic random number generator using finite field operations
- Patent number 8,250,129
- Issue date Aug 21, 2012
- LSI Corporation
- Sergey Gribok
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable Reed-Solomon decoder based on modified Forney syndromes
- Patent number 8,181,096
- Issue date May 15, 2012
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable low-density parity-check decoder for LDPC codes of arb...
- Patent number 8,151,160
- Issue date Apr 3, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory mapping for parallel turbo decoding
- Patent number 8,132,075
- Issue date Mar 6, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for assigning code blocks to constituent decoder...
- Patent number 8,095,845
- Issue date Jan 10, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for programmable decoding of a plurality of c...
- Patent number 8,035,537
- Issue date Oct 11, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for outputting a sequence of commands and data de...
- Patent number 8,006,209
- Issue date Aug 23, 2011
- LSI Corporation
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel LDPC decoder
- Patent number 7,934,139
- Issue date Apr 26, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low complexity LDPC encoding algorithm
- Patent number 7,913,149
- Issue date Mar 22, 2011
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Built in test controller with a downloadable testing program
- Patent number 7,882,406
- Issue date Feb 1, 2011
- LSI Corporation
- Alexander E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Decision tree representation of a function
- Patent number 7,877,724
- Issue date Jan 25, 2011
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command language for memory testing
- Patent number 7,856,577
- Issue date Dec 21, 2010
- LSI Corporation
- Alexander E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital Gaussian noise simulator
- Patent number 7,822,099
- Issue date Oct 26, 2010
- LSI Corporation
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low area architecture in BCH decoder
- Patent number 7,823,050
- Issue date Oct 26, 2010
- LSICorporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Density driven layout for RRAM configuration module
- Patent number 7,818,703
- Issue date Oct 19, 2010
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance tiling for RRAM memory
- Patent number 7,739,471
- Issue date Jun 15, 2010
- LSI Corporation
- Alexander Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipelined LDPC arithmetic unit
- Patent number 7,739,575
- Issue date Jun 15, 2010
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for fast unbalanced pipeline architecture
- Patent number 7,667,494
- Issue date Feb 23, 2010
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer-deserializer (SerDes) having a predominantly digital arc...
- Patent number 7,656,325
- Issue date Feb 2, 2010
- LSI Corporation
- Alexander E. Andreev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Circuits And Methods For Routing Crossbars With Programmable Vias
- Publication number 20220014197
- Publication date Jan 13, 2022
- Intel Corporation
- Atul Maheshwari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Configurable Clock Macro Circuits And Methods
- Publication number 20220004221
- Publication date Jan 6, 2022
- Intel Corporation
- Alexander Rusakov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA...
- Publication number 20160293541
- Publication date Oct 6, 2016
- eASIC Corporation
- Alexander ANDREEV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Architectural Floorplan for a Structured ASIC Manufactured on a 28...
- Publication number 20140103959
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS...
- Publication number 20140105246
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- G01 - MEASURING TESTING
Information Patent Application
Digitally Controlled Delay Line for a Structured ASIC Having a Via...
- Publication number 20140103985
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Via-Configurable High-Performance Logic Block Involving Transistor...
- Publication number 20140028348
- Publication date Jan 30, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable Node Processing Unit
- Publication number 20130254252
- Publication date Sep 26, 2013
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cryptographic Random Number Generator Using Finite Field Operations
- Publication number 20120278372
- Publication date Nov 1, 2012
- LSI Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Via-Configurable High-Performance Logic Block Architecture
- Publication number 20120161093
- Publication date Jun 28, 2012
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER...
- Publication number 20120079345
- Publication date Mar 29, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Parallel LDPC Decoder
- Publication number 20110173510
- Publication date Jul 14, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Complexity LDPC Encoding Algorithm
- Publication number 20110099454
- Publication date Apr 28, 2011
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITEC...
- Publication number 20100162071
- Publication date Jun 24, 2010
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for using the universal multipole for the impleme...
- Publication number 20100031126
- Publication date Feb 4, 2010
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Variable Node Processing Unit
- Publication number 20100030835
- Publication date Feb 4, 2010
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERAS...
- Publication number 20100031127
- Publication date Feb 4, 2010
- Pavel A. Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...
- Publication number 20090309770
- Publication date Dec 17, 2009
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Computational Architecture for Soft Decoding
- Publication number 20090287980
- Publication date Nov 19, 2009
- LSI Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decision Tree Representation of a Function
- Publication number 20090281969
- Publication date Nov 12, 2009
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE
- Publication number 20090243657
- Publication date Oct 1, 2009
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES
- Publication number 20090158118
- Publication date Jun 18, 2009
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMMAND LANGUAGE FOR MEMORY TESTING
- Publication number 20090133003
- Publication date May 21, 2009
- LSI Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for outputting a sequence of commands and data de...
- Publication number 20090094571
- Publication date Apr 9, 2009
- LSI CORPORATION
- Andrey A. Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cryptographic random number generator using finite field operations
- Publication number 20080320066
- Publication date Dec 25, 2008
- LSI Logic Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED LDPC ARITHMETIC UNIT
- Publication number 20080178057
- Publication date Jul 24, 2008
- LSI Logic Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Complexity LDPC Encoding Algorithm
- Publication number 20080168334
- Publication date Jul 10, 2008
- LSI Logic Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Area Architecture in BCH Decoder
- Publication number 20080155381
- Publication date Jun 26, 2008
- LSI Logic Corporation
- Elyar E. Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Parallel LDPC Decoder
- Publication number 20080134008
- Publication date Jun 5, 2008
- LSI Logic Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Built in self test transport controller architecture
- Publication number 20080109688
- Publication date May 8, 2008
- LSI Logic Corporation
- Sergey Gribok
- G11 - INFORMATION STORAGE

Alexander E. Andreev

Person

Patents Grantslast 30 patents

Variable node processing unit

Architectural floorplan for a structured ASIC manufactured on a 28...

Via-configurable high-performance logic block involving transistor...

System and method for assigning code blocks to constituent decoder...

Via-configurable high-performance logic block architecture

Microcontroller controlled or direct mode controlled network-fabric...

Clock network fishbone architecture for a structured ASIC manufactu...

System and method for using the universal multipole for the impleme...

Variable node processing unit

Circuits for implementing parity computation in a parallel architec...

Scheme for erasure locator polynomial calculation in error-and-eras...

Cryptographic random number generator using finite field operations

Configurable Reed-Solomon decoder based on modified Forney syndromes

Configurable low-density parity-check decoder for LDPC codes of arb...

Memory mapping for parallel turbo decoding

System and method for assigning code blocks to constituent decoder...

Methods and apparatus for programmable decoding of a plurality of c...

Method and system for outputting a sequence of commands and data de...

Parallel LDPC decoder

Low complexity LDPC encoding algorithm

Built in test controller with a downloadable testing program

Decision tree representation of a function

Command language for memory testing

Digital Gaussian noise simulator

Low area architecture in BCH decoder

Density driven layout for RRAM configuration module

High performance tiling for RRAM memory

Pipelined LDPC arithmetic unit

Methods and apparatus for fast unbalanced pipeline architecture

Serializer-deserializer (SerDes) having a predominantly digital arc...

Patents Applicationslast 30 patents

Circuits And Methods For Routing Crossbars With Programmable Vias

Configurable Clock Macro Circuits And Methods

STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA...

Architectural Floorplan for a Structured ASIC Manufactured on a 28...

Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS...

Digitally Controlled Delay Line for a Structured ASIC Having a Via...

Via-Configurable High-Performance Logic Block Involving Transistor...

Variable Node Processing Unit

Cryptographic Random Number Generator Using Finite Field Operations

Via-Configurable High-Performance Logic Block Architecture

SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER...

Parallel LDPC Decoder

Low Complexity LDPC Encoding Algorithm

CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITEC...

System and method for using the universal multipole for the impleme...

Variable Node Processing Unit

SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERAS...

METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...

Computational Architecture for Soft Decoding

Decision Tree Representation of a Function

METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE

CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES

COMMAND LANGUAGE FOR MEMORY TESTING

Method and system for outputting a sequence of commands and data de...

Cryptographic random number generator using finite field operations

PIPELINED LDPC ARITHMETIC UNIT

Low Complexity LDPC Encoding Algorithm

Low Area Architecture in BCH Decoder

Parallel LDPC Decoder

Built in self test transport controller architecture