Alexander George

Person

Durham, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed command and address bus architecture for a memory modul...
- Patent number 8,161,219
- Issue date Apr 17, 2012
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus termination system and method
- Patent number 8,041,865
- Issue date Oct 18, 2011
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-component module fly-by output alignment arrangement and method
- Patent number 7,873,857
- Issue date Jan 18, 2011
- Qimonda AG
- Ronald Baker
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory architecture
- Patent number 7,848,153
- Issue date Dec 7, 2010
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Horizontal dual in-line memory modules
- Patent number 7,771,206
- Issue date Aug 10, 2010
- Qimonda AG
- Michael Bruennert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Implementation of a fusing scheme to allow internal voltage trimming
- Patent number 7,539,075
- Issue date May 26, 2009
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Grant
Maintaining internal voltages of an integrated circuit in response...
- Patent number 7,345,931
- Issue date Mar 18, 2008
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementation of a fusing scheme to allow internal voltage trimming
- Patent number 7,277,350
- Issue date Oct 2, 2007
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal voltage generator with temperature control
- Patent number 7,266,031
- Issue date Sep 4, 2007
- Infineon Technologies AG
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to improve current and slew rate ratio of off-chip drivers
- Patent number 7,265,585
- Issue date Sep 4, 2007
- Infineon Technologies AG
- Thoai Thai Le
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Disabling clocked standby mode based on device temperature
- Patent number 7,177,219
- Issue date Feb 13, 2007
- Infineon Technologies AG
- David Herbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with post-amble data strobe signal noise rejec...
- Patent number 7,031,205
- Issue date Apr 18, 2006
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of reading data from a memory device
- Patent number 6,970,395
- Issue date Nov 29, 2005
- Infineon Technologies AG
- Thoai-Thai Le
- G11 - INFORMATION STORAGE
Information Patent Grant
Self alignment system for complement clocks
- Patent number 6,946,889
- Issue date Sep 20, 2005
- Infineon Technologies AG
- Thoai-Thai Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor wafer testing system
- Patent number 6,888,365
- Issue date May 3, 2005
- Infineon Technologies North America Corporation
- Daivid Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Grant
System and method for monitoring internal voltages on an integrated...
- Patent number 6,845,048
- Issue date Jan 18, 2005
- Infineon Technologies AG
- George W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementation of a temperature sensor to control internal chip vol...
- Patent number 6,809,978
- Issue date Oct 26, 2004
- Infineon Technologies AG
- George William Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay lock loop having an edge detector and fixed delay
- Patent number 6,777,990
- Issue date Aug 17, 2004
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic delay line control
- Patent number 6,765,419
- Issue date Jul 20, 2004
- Infineon Technologies AG
- George W. Alexander
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DQS postamble noise suppression by forcing a minimum pulse length
- Patent number 6,760,261
- Issue date Jul 6, 2004
- Infineon Technologies AG
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay lock loop having a variable voltage regulator
- Patent number 6,693,473
- Issue date Feb 17, 2004
- Infineon Technologies AG
- George W. Alexander
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a delay lock loop
- Patent number 6,653,875
- Issue date Nov 25, 2003
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-adjusting clock phase controlled architecture
- Patent number 6,516,006
- Issue date Feb 4, 2003
- Mitsubishi Electric & Electronics USA, Inc.
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Distributed Command and Address Bus Architecture
- Publication number 20100082871
- Publication date Apr 1, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Horizontal Dual In-line Memory Modules
- Publication number 20100062621
- Publication date Mar 11, 2010
- MICHAEL BRUENNERT
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High Speed Memory Architecture
- Publication number 20100046266
- Publication date Feb 25, 2010
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked Memory Module
- Publication number 20100032820
- Publication date Feb 11, 2010
- Michael Bruennert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bus Termination System and Method
- Publication number 20100030934
- Publication date Feb 4, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITALLY CONTROLLED DELAY ELEMENT
- Publication number 20090115484
- Publication date May 7, 2009
- GEORGE ALEXANDER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-Component Module Fly-By Output Alignment Arrangement and Method
- Publication number 20080177911
- Publication date Jul 24, 2008
- QIMONDA NORTH AMERICA CORP.
- Ronald Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING
- Publication number 20080008012
- Publication date Jan 10, 2008
- Infineon Technologies AG
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Application
Test modes for a semiconductor integrated circuit device
- Publication number 20070046308
- Publication date Mar 1, 2007
- Ronald Baker
- G01 - MEASURING TESTING
Information Patent Application
Maintaining internal voltages of an integrated circuit in response...
- Publication number 20070025163
- Publication date Feb 1, 2007
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE
- Publication number 20070019489
- Publication date Jan 25, 2007
- David Herbert
- G11 - INFORMATION STORAGE
Information Patent Application
Implementation of a fusing scheme to allow internal voltage trimming
- Publication number 20060274594
- Publication date Dec 7, 2006
- Jennifer Faye Huckaby
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory with post-amble data strobe signal noise rejec...
- Publication number 20060168470
- Publication date Jul 27, 2006
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Application
Method to improve current and slew rate ratio of off-chip drivers
- Publication number 20060125520
- Publication date Jun 15, 2006
- Thoai Thai Le
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Internal voltage generator with temperature control
- Publication number 20050105367
- Publication date May 19, 2005
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory with post-amble data strobe signal noise rejec...
- Publication number 20050068810
- Publication date Mar 31, 2005
- Infineon Technologies North America Corp.
- Jonghee Han
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device and method of reading data from a memory device
- Publication number 20050052943
- Publication date Mar 10, 2005
- Thoai-Thai Le
- G11 - INFORMATION STORAGE
Information Patent Application
Self alignment system for complement clocks
- Publication number 20040160253
- Publication date Aug 19, 2004
- Thoai-Thai Le
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DQS postamble noise suppression by forcing a minimum pulse length
- Publication number 20040056697
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- Torsten Partsch
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for monitoring internal voltages on an integrated...
- Publication number 20040057289
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- George W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor die isolation system
- Publication number 20040051550
- Publication date Mar 18, 2004
- David Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor wafer testing system
- Publication number 20040051547
- Publication date Mar 18, 2004
- Daivid Suitwai Ma
- G01 - MEASURING TESTING
Information Patent Application
Implementation of a temperature sensor to control internal chip vol...
- Publication number 20030210598
- Publication date Nov 13, 2003
- George William Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
Delay lock loop having a variable voltage regulator
- Publication number 20030179026
- Publication date Sep 25, 2003
- Infineon Technologies North America Corp.
- George W. Alexander
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay lock loop having an edge detector and fixed delay
- Publication number 20030179025
- Publication date Sep 25, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR A DELAY LOCK LOOP
- Publication number 20030169085
- Publication date Sep 11, 2003
- Infineon Technologies North America Corp.
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DELAY LINE CONTROL
- Publication number 20030169083
- Publication date Sep 11, 2003
- Infineon Technologies North America Corp.
- George W. Alexander
- H03 - BASIC ELECTRONIC CIRCUITRY

Alexander George

Person

Patents Grantslast 30 patents

Distributed command and address bus architecture for a memory modul...

Bus termination system and method

Multi-component module fly-by output alignment arrangement and method

High speed memory architecture

Horizontal dual in-line memory modules

Implementation of a fusing scheme to allow internal voltage trimming

Maintaining internal voltages of an integrated circuit in response...

Implementation of a fusing scheme to allow internal voltage trimming

Internal voltage generator with temperature control

Method to improve current and slew rate ratio of off-chip drivers

Disabling clocked standby mode based on device temperature

Random access memory with post-amble data strobe signal noise rejec...

Memory device and method of reading data from a memory device

Self alignment system for complement clocks

Semiconductor wafer testing system

System and method for monitoring internal voltages on an integrated...

Implementation of a temperature sensor to control internal chip vol...

Delay lock loop having an edge detector and fixed delay

Dynamic delay line control

DQS postamble noise suppression by forcing a minimum pulse length

Delay lock loop having a variable voltage regulator

Method and apparatus for a delay lock loop

Self-adjusting clock phase controlled architecture

Patents Applicationslast 30 patents

Distributed Command and Address Bus Architecture

Horizontal Dual In-line Memory Modules

High Speed Memory Architecture

Stacked Memory Module

Bus Termination System and Method

DIGITALLY CONTROLLED DELAY ELEMENT

Multi-Component Module Fly-By Output Alignment Arrangement and Method

IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING

Test modes for a semiconductor integrated circuit device

Maintaining internal voltages of an integrated circuit in response...

DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE

Implementation of a fusing scheme to allow internal voltage trimming

Random access memory with post-amble data strobe signal noise rejec...

Method to improve current and slew rate ratio of off-chip drivers

Internal voltage generator with temperature control

Random access memory with post-amble data strobe signal noise rejec...

Memory device and method of reading data from a memory device

Self alignment system for complement clocks

DQS postamble noise suppression by forcing a minimum pulse length

System and method for monitoring internal voltages on an integrated...

Semiconductor die isolation system

Semiconductor wafer testing system

Implementation of a temperature sensor to control internal chip vol...

Delay lock loop having a variable voltage regulator

Delay lock loop having an edge detector and fixed delay

METHOD AND APPARATUS FOR A DELAY LOCK LOOP

DYNAMIC DELAY LINE CONTROL