Alexander Tetelbaum

Person

Hayward, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Extraction tool and method for determining maximum and minimum stag...
- Patent number 8,799,839
- Issue date Aug 5, 2014
- LSI Corporation
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of core timing prediction of core logic in the...
- Patent number 8,775,995
- Issue date Jul 8, 2014
- LSI Corporation
- Ruben Salvador Molina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing and checking electronic circuits with flexible ramptim...
- Patent number 8,694,937
- Issue date Apr 8, 2014
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit timing analysis incorporating the effects of temperature in...
- Patent number 8,645,888
- Issue date Feb 4, 2014
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for designing integrated circuits that employ ada...
- Patent number 8,539,424
- Issue date Sep 17, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing signoff system and method that takes static and dynamic volt...
- Patent number 8,516,424
- Issue date Aug 20, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing error sampling generator and a method of timing testing
- Patent number 8,473,890
- Issue date Jun 25, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent dummy metal fill process for integrated circuits
- Patent number 8,397,196
- Issue date Mar 12, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing and checking electronic circuits with flexible ramptim...
- Patent number 8,332,792
- Issue date Dec 11, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of core timing prediction of core logic in the...
- Patent number 8,321,826
- Issue date Nov 27, 2012
- LSI Corporation
- Ruben Salvador Molina, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing path delay sensitivity to temperature variation in timing-...
- Patent number 8,225,257
- Issue date Jul 17, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing error sampling generator, critical path monitor for hold and...
- Patent number 8,191,029
- Issue date May 29, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit timing analysis incorporating the effects of temperature in...
- Patent number 8,181,144
- Issue date May 15, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic design automation tool and method for optimizing the pla...
- Patent number 8,010,935
- Issue date Aug 30, 2011
- LSI Corporation
- Alexander Tetelbaum
- G01 - MEASURING TESTING
Information Patent Grant
System and method for reducing the generation of inconsequential vi...
- Patent number 7,971,169
- Issue date Jun 28, 2011
- LSI Corporation
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of core timing prediction of core logic in the...
- Patent number 7,739,639
- Issue date Jun 15, 2010
- LSI Corporation
- Ruben Salvador Molina, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for static timing analysis with delay d...
- Patent number 7,480,881
- Issue date Jan 20, 2009
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for detailed routing of an integrated c...
- Patent number 7,370,309
- Issue date May 6, 2008
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of estimating a total path delay in an integrated circuit de...
- Patent number 7,213,223
- Issue date May 1, 2007
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for estimating speed-up and slow-down n...
- Patent number 7,178,121
- Issue date Feb 13, 2007
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of floorplanning and cell placement for integrated circuit c...
- Patent number 7,174,524
- Issue date Feb 6, 2007
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of finding critical nets in an integrated circuit design
- Patent number 7,107,558
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimal bends connection models for wire density calculation
- Patent number 7,076,406
- Issue date Jul 11, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automated repair of crosstalk violations and timing viola...
- Patent number 7,062,737
- Issue date Jun 13, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of noise analysis and correction of noise violations for an...
- Patent number 7,062,731
- Issue date Jun 13, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent crosstalk delay estimator for integrated circuit design...
- Patent number 7,043,708
- Issue date May 9, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of clock driven cell placement and clock tree synthesis for...
- Patent number 7,039,891
- Issue date May 2, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a co-axial wire in a semicond...
- Patent number 7,015,569
- Issue date Mar 21, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intelligent engine for protection against injected crosstalk delay
- Patent number 6,948,142
- Issue date Sep 20, 2005
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated design system and method for reducing and avoiding cross...
- Patent number 6,907,586
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Maad A. Al-Dabagh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Circuit Timing Analysis Incorporating the Effects of Temperature In...
- Publication number 20140089881
- Publication date Mar 27, 2014
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR TAKING INTER-CLOCK CORRELATION INTO ACCOUNT I...
- Publication number 20130239079
- Publication date Sep 12, 2013
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING
- Publication number 20130152034
- Publication date Jun 13, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING SIGNOFF FOR MAXIMUM PROFIT
- Publication number 20130080198
- Publication date Mar 28, 2013
- LSI Corporation
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIM...
- Publication number 20130080988
- Publication date Mar 28, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLT...
- Publication number 20130080986
- Publication date Mar 28, 2013
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE...
- Publication number 20130043602
- Publication date Feb 21, 2013
- LSI Corporation
- Rube Salvador Molina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS
- Publication number 20120284679
- Publication date Nov 8, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING
- Publication number 20120278780
- Publication date Nov 1, 2012
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Timing Analysis Incorporating the Effects of Temperature In...
- Publication number 20120210287
- Publication date Aug 16, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIM...
- Publication number 20120017190
- Publication date Jan 19, 2012
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF CHARACTERIZING REGULAR ELECTRONIC CIRCUITS
- Publication number 20120011483
- Publication date Jan 12, 2012
- LSI Corporation
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADA...
- Publication number 20110138347
- Publication date Jun 9, 2011
- ICERA INC.
- Alexander Y. Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE...
- Publication number 20100289112
- Publication date Nov 18, 2010
- LSI Corporation
- Ruben Salvador Molina, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND...
- Publication number 20100153895
- Publication date Jun 17, 2010
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Timing Analysis Incorporating the Effects of Temperature In...
- Publication number 20100095259
- Publication date Apr 15, 2010
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Path Delay Sensitivity to Temperature Variation in Timing-...
- Publication number 20100095260
- Publication date Apr 15, 2010
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLA...
- Publication number 20090282381
- Publication date Nov 12, 2009
- LSI Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY D...
- Publication number 20080046848
- Publication date Feb 21, 2008
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for detailed routing of an integrated c...
- Publication number 20070079274
- Publication date Apr 5, 2007
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for estimating speed-up and slow-down n...
- Publication number 20060294482
- Publication date Dec 28, 2006
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of estimating a total path delay in an integrated circuit de...
- Publication number 20060112158
- Publication date May 25, 2006
- LS Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of floorplanning and cell placement for integrated circuit c...
- Publication number 20060064662
- Publication date Mar 23, 2006
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICOND...
- Publication number 20060043541
- Publication date Mar 2, 2006
- Alexander Tetelbaum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of automated repair of crosstalk violations and timing viola...
- Publication number 20060026539
- Publication date Feb 2, 2006
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of noise analysis and correction of noise violations for an...
- Publication number 20050060675
- Publication date Mar 17, 2005
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of clock driven cell placement and clock tree synthesis for...
- Publication number 20050050497
- Publication date Mar 3, 2005
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of finding critical nets in an integrated circuit design
- Publication number 20050022145
- Publication date Jan 27, 2005
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intelligent crosstalk delay estimator for integrated circuit design...
- Publication number 20040250225
- Publication date Dec 9, 2004
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Intelligent engine for protection against injected crosstalk delay
- Publication number 20040243956
- Publication date Dec 2, 2004
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING

Alexander Tetelbaum

Person

Patents Grantslast 30 patents

Extraction tool and method for determining maximum and minimum stag...

Method and apparatus of core timing prediction of core logic in the...

Implementing and checking electronic circuits with flexible ramptim...

Circuit timing analysis incorporating the effects of temperature in...

System and method for designing integrated circuits that employ ada...

Timing signoff system and method that takes static and dynamic volt...

Timing error sampling generator and a method of timing testing

Intelligent dummy metal fill process for integrated circuits

Implementing and checking electronic circuits with flexible ramptim...

Method and apparatus of core timing prediction of core logic in the...

Reducing path delay sensitivity to temperature variation in timing-...

Timing error sampling generator, critical path monitor for hold and...

Circuit timing analysis incorporating the effects of temperature in...

Electronic design automation tool and method for optimizing the pla...

System and method for reducing the generation of inconsequential vi...

Method and apparatus of core timing prediction of core logic in the...

Method and computer program for static timing analysis with delay d...

Method and computer program for detailed routing of an integrated c...

Method of estimating a total path delay in an integrated circuit de...

Method and computer program for estimating speed-up and slow-down n...

Method of floorplanning and cell placement for integrated circuit c...

Method of finding critical nets in an integrated circuit design

Minimal bends connection models for wire density calculation

Method of automated repair of crosstalk violations and timing viola...

Method of noise analysis and correction of noise violations for an...

Intelligent crosstalk delay estimator for integrated circuit design...

Method of clock driven cell placement and clock tree synthesis for...

Method and apparatus for implementing a co-axial wire in a semicond...

Intelligent engine for protection against injected crosstalk delay

Integrated design system and method for reducing and avoiding cross...

Patents Applicationslast 30 patents

Circuit Timing Analysis Incorporating the Effects of Temperature In...

SYSTEM AND METHOD FOR TAKING INTER-CLOCK CORRELATION INTO ACCOUNT I...

SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING

TIMING SIGNOFF FOR MAXIMUM PROFIT

IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIM...

TIMING SIGNOFF SYSTEM AND METHOD THAT TAKES STATIC AND DYNAMIC VOLT...

METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE...

INTELLIGENT DUMMY METAL FILL PROCESS FOR INTEGRATED CIRCUITS

TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING

Circuit Timing Analysis Incorporating the Effects of Temperature In...

IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIM...

METHOD OF CHARACTERIZING REGULAR ELECTRONIC CIRCUITS

SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADA...

METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE...

TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND...

Circuit Timing Analysis Incorporating the Effects of Temperature In...

Reducing Path Delay Sensitivity to Temperature Variation in Timing-...

ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLA...

METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY D...

Method and computer program for detailed routing of an integrated c...

Method and computer program for estimating speed-up and slow-down n...

Method of estimating a total path delay in an integrated circuit de...

Method of floorplanning and cell placement for integrated circuit c...

METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICOND...

Method of automated repair of crosstalk violations and timing viola...

Method of noise analysis and correction of noise violations for an...

Method of clock driven cell placement and clock tree synthesis for...

Method of finding critical nets in an integrated circuit design

Intelligent crosstalk delay estimator for integrated circuit design...

Intelligent engine for protection against injected crosstalk delay