Antonio R. Pelella

Person

Highland Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Local bit select with improved fast read before write suppression
- Patent number 11,682,452
- Issue date Jun 20, 2023
- International Business Machines Corporation
- Antonio Pelella
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit low power application
- Patent number 10,454,477
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Antonio Raffaele Pelella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit low power application
- Patent number 10,374,604
- Issue date Aug 6, 2019
- International Business Machines Corporation
- Antonio Raffaele Pelella
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 10,367,507
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control method
- Patent number 10,320,388
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control method
- Patent number 10,312,915
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit with delayed precharge
- Patent number 10,312,916
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 10,224,933
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 9,966,958
- Issue date May 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic decode circuit with active glitch control
- Patent number 9,742,408
- Issue date Aug 22, 2017
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Global bit select circuit with write around capability
- Patent number 8,638,595
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Antonio R. Pelella
- G11 - INFORMATION STORAGE
Information Patent Grant
Single clock dynamic compare circuit
- Patent number 8,233,331
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust local bit select circuitry to overcome timing mismatch
- Patent number 8,184,475
- Issue date May 22, 2012
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance pseudo dynamic pulse controllable multiplexer
- Patent number 7,592,851
- Issue date Sep 22, 2009
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Global bit select circuit interface with dual read and write bit li...
- Patent number 7,463,537
- Issue date Dec 9, 2008
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Global bit select circuit with dual read and write bit line pairs
- Patent number 7,336,546
- Issue date Feb 26, 2008
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Split L2 latch with glitch free programmable delay
- Patent number 7,293,209
- Issue date Nov 6, 2007
- International Business Machines Corporation
- Yuen H. Chan
- G01 - MEASURING TESTING
Information Patent Grant
Global bit line restore timing scheme and circuit
- Patent number 7,272,030
- Issue date Sep 18, 2007
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM and dual single ended bit sense for an SRAM
- Patent number 7,170,799
- Issue date Jan 30, 2007
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Global bit line restore timing scheme and circuit
- Patent number 7,170,774
- Issue date Jan 30, 2007
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit select with suppression of fast read before write
- Patent number 7,113,433
- Issue date Sep 26, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit select circuit with slow read recovery scheme
- Patent number 7,102,946
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Antonio R. Pelella
- G11 - INFORMATION STORAGE
Information Patent Grant
Output driver with pulse to static converter
- Patent number 7,084,673
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Cache late select circuit
- Patent number 7,054,184
- Issue date May 30, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Coupled body contacts for SOI differential circuits
- Patent number 6,868,000
- Issue date Mar 15, 2005
- International Business Machines Corp.
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance dual-stage sense amplifier circuit
- Patent number 6,788,112
- Issue date Sep 7, 2004
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Self timed pre-charged address compare logic circuit
- Patent number 6,646,544
- Issue date Nov 11, 2003
- International Business Machines Corporation
- Antonio R. Pelella
- G05 - CONTROLLING REGULATING
Information Patent Grant
Two stage SRCMOS sense amplifier
- Patent number 5,982,203
- Issue date Nov 9, 1999
- International Business Machines Corporation
- Antonio R. Pelella
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for a fast scan GRA cell circuit
- Patent number 5,764,656
- Issue date Jun 9, 1998
- International Business Machines Corporation
- Antonio Raffaele Pelella
- C07 - ORGANIC CHEMISTRY
Information Patent Grant
Fast scan GRA cell circuit
- Patent number 5,748,643
- Issue date May 5, 1998
- International Business Machines Corporation
- Antonio Raffaele Pelella
- C07 - ORGANIC CHEMISTRY

Patents Applicationslast 30 patents

Information Patent Application
LOCAL BIT SELECT WITH IMPROVED FAST READ BEFORE WRITE SUPPRESSION
- Publication number 20230086799
- Publication date Mar 23, 2023
- International Business Machines Corporation
- Antonio PELELLA
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180367145
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL METHOD
- Publication number 20180323786
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH DELAYED PRECHARGE
- Publication number 20180323787
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL Method
- Publication number 20180316354
- Publication date Nov 1, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180091152
- Publication date Mar 29, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL
- Publication number 20180091153
- Publication date Mar 29, 2018
- International Business Machines Corporation
- Paul Alan Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
GLOBAL BIT SELECT CIRCUIT WITH WRITE AROUND CAPABILITY
- Publication number 20130272057
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Antonio R. Pelella
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Circuit Arrangement for Performing a Write Through Opera...
- Publication number 20110317478
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE CLOCK DYNAMIC COMPARE CIRCUIT
- Publication number 20110298500
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY
- Publication number 20110296259
- Publication date Dec 1, 2011
- International Business Machines Corporation
- Bargav Balakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST LOCAL BIT SELECT CIRCUITRY TO OVERCOME TIMING MISMATCH
- Publication number 20110199817
- Publication date Aug 18, 2011
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH PERFORMANCE PSEUDO DYNAMIC PULSE CONTROLLABLE MULTIPLEXER
- Publication number 20090189675
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Global Bit Select Circuit Interface with Dual Read and Write Bit Li...
- Publication number 20080056052
- Publication date Mar 6, 2008
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Global Bit Line Restore Timing Scheme and Circuit
- Publication number 20070058421
- Publication date Mar 15, 2007
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL BIT SELECT CIRCUIT WITH SLOW READ RECOVERY SCHEME
- Publication number 20060176728
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Antonio R. Pelella
- G11 - INFORMATION STORAGE
Information Patent Application
Split L2 latch with glitch free programmable delay
- Publication number 20060179375
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G01 - MEASURING TESTING
Information Patent Application
SRAM and dual single ended bit sense for an SRAM
- Publication number 20060176732
- Publication date Aug 10, 2006
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Global bit select circuit with dual read and write bit line pairs
- Publication number 20060176753
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Local bit select with suppression of fast read before write
- Publication number 20060176729
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Global bit line restore timing scheme and circuit
- Publication number 20060176730
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Output driver with pulse to static converter
- Publication number 20050253639
- Publication date Nov 17, 2005
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Cache late select circuit
- Publication number 20050254285
- Publication date Nov 17, 2005
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
Coupled body contacts for SOI differential circuits
- Publication number 20040228160
- Publication date Nov 18, 2004
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Application
SELF TIMED PRE-CHARGED ADDRESS COMPARE LOGIC CIRCUIT
- Publication number 20030210134
- Publication date Nov 13, 2003
- International Business Machines Corporation
- Antonio R. Pelella
- G05 - CONTROLLING REGULATING

Antonio R. Pelella

Person

Patents Grantslast 30 patents

Local bit select with improved fast read before write suppression

Dynamic decode circuit low power application

Dynamic decode circuit low power application

Dynamic decode circuit with active glitch control

Dynamic decode circuit with active glitch control method

Dynamic decode circuit with active glitch control method

Dynamic decode circuit with delayed precharge

Dynamic decode circuit with active glitch control

Dynamic decode circuit with active glitch control

Dynamic decode circuit with active glitch control

Global bit select circuit with write around capability

Single clock dynamic compare circuit

Robust local bit select circuitry to overcome timing mismatch

High performance pseudo dynamic pulse controllable multiplexer

Global bit select circuit interface with dual read and write bit li...

Global bit select circuit with dual read and write bit line pairs

Split L2 latch with glitch free programmable delay

Global bit line restore timing scheme and circuit

SRAM and dual single ended bit sense for an SRAM

Global bit line restore timing scheme and circuit

Local bit select with suppression of fast read before write

Local bit select circuit with slow read recovery scheme

Output driver with pulse to static converter

Cache late select circuit

Coupled body contacts for SOI differential circuits

High performance dual-stage sense amplifier circuit

Self timed pre-charged address compare logic circuit

Two stage SRCMOS sense amplifier

Method for a fast scan GRA cell circuit

Fast scan GRA cell circuit

Patents Applicationslast 30 patents

LOCAL BIT SELECT WITH IMPROVED FAST READ BEFORE WRITE SUPPRESSION

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL METHOD

DYNAMIC DECODE CIRCUIT WITH DELAYED PRECHARGE

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL Method

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

DYNAMIC DECODE CIRCUIT WITH ACTIVE GLITCH CONTROL

GLOBAL BIT SELECT CIRCUIT WITH WRITE AROUND CAPABILITY

Method and Circuit Arrangement for Performing a Write Through Opera...

SINGLE CLOCK DYNAMIC COMPARE CIRCUIT

TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY

ROBUST LOCAL BIT SELECT CIRCUITRY TO OVERCOME TIMING MISMATCH

HIGH PERFORMANCE PSEUDO DYNAMIC PULSE CONTROLLABLE MULTIPLEXER

Global Bit Select Circuit Interface with Dual Read and Write Bit Li...

Global Bit Line Restore Timing Scheme and Circuit

LOCAL BIT SELECT CIRCUIT WITH SLOW READ RECOVERY SCHEME

Split L2 latch with glitch free programmable delay

SRAM and dual single ended bit sense for an SRAM

Global bit select circuit with dual read and write bit line pairs

Local bit select with suppression of fast read before write

Global bit line restore timing scheme and circuit

Output driver with pulse to static converter

Cache late select circuit

Coupled body contacts for SOI differential circuits

SELF TIMED PRE-CHARGED ADDRESS COMPARE LOGIC CIRCUIT