Anupama Bowonder

Person

Berkeley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 12,021,149
- Issue date Jun 25, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel structures with sub-fin dopant diffusion blocking layers
- Patent number 11,984,449
- Issue date May 14, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-fin leakage reduction for template strained materials
- Patent number 11,923,412
- Issue date Mar 5, 2024
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin shaping and integrated circuit structures resulting therefrom
- Patent number 11,901,457
- Issue date Feb 13, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial oxide plug for strained transistors
- Patent number 11,757,037
- Issue date Sep 12, 2023
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures with source or drain dopant diffusion...
- Patent number 11,735,630
- Issue date Aug 22, 2023
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 11,682,731
- Issue date Jun 20, 2023
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-fin leakage reduction for template strained materials
- Patent number 11,600,696
- Issue date Mar 7, 2023
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel structures with sub-fin dopant diffusion blocking layers
- Patent number 11,521,968
- Issue date Dec 6, 2022
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple strain states in epitaxial transistor channel through the...
- Patent number 11,495,683
- Issue date Nov 8, 2022
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures having asymmetric source and drain st...
- Patent number 11,462,536
- Issue date Oct 4, 2022
- Intel Corporation
- Anupama Bowonder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge architecture with alternate channel material
- Patent number 11,456,357
- Issue date Sep 27, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried etch-stop layer to help control transistor source/drain depth
- Patent number 11,430,868
- Issue date Aug 30, 2022
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with contact etch stop layer
- Patent number 11,374,100
- Issue date Jun 28, 2022
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial oxide plug for strained transistors
- Patent number 11,251,302
- Issue date Feb 15, 2022
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor layer between source/drain regions and gate spacers
- Patent number 11,152,461
- Issue date Oct 19, 2021
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with channel and sub-channel regions with distinct comp...
- Patent number 11,069,795
- Issue date Jul 20, 2021
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for forming dual-strain fins for co-integrated n-MOS and...
- Patent number 10,886,272
- Issue date Jan 5, 2021
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tunneling transistor suitable for low voltage operation
- Patent number 9,117,893
- Issue date Aug 25, 2015
- The Regents of the University of California
- Chenming Hu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Tunneling transistor suitable for low voltage operation
- Patent number 8,384,122
- Issue date Feb 26, 2013
- The Regents of the University of California
- Chenming Hu
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
MODULATION OF CHIP PERFORMANCE BY CONTROLLING TRANSISTOR GATE PROFILE
- Publication number 20240332088
- Publication date Oct 3, 2024
- Intel Corporation
- Reza Bayati
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20240274718
- Publication date Aug 15, 2024
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CUT, AND SOURCE AND DRAIN CONTACTS
- Publication number 20240222447
- Publication date Jul 4, 2024
- Intel Corporation
- Reken Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL GATE CUT WITH HYBRID MATERIAL FILL
- Publication number 20240213100
- Publication date Jun 27, 2024
- Intel Corporation
- Swapnadip Ghosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTR...
- Publication number 20230420574
- Publication date Dec 28, 2023
- Intel Corporation
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION...
- Publication number 20230343826
- Publication date Oct 26, 2023
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20230275157
- Publication date Aug 31, 2023
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH EPITAXIAL SOURCE/DRAIN LINER FOR IMPROVED CONTACT...
- Publication number 20230197716
- Publication date Jun 22, 2023
- Intel Corporation
- Cory C. Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS
- Publication number 20230187492
- Publication date Jun 15, 2023
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20230131126
- Publication date Apr 27, 2023
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL STRUCTURES WITH SUB-FIN DOPANT DIFFUSION BLOCKING LAYERS
- Publication number 20230043665
- Publication date Feb 9, 2023
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CONTACT RESISTIVITY WITH PMOS GERMANIUM AND SILICON DOPED W...
- Publication number 20220416043
- Publication date Dec 29, 2022
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS
- Publication number 20220131007
- Publication date Apr 28, 2022
- Intel Corporation
- Karthik JAMBUNATHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE STRAIN STATES IN EPITAXIAL TRANSISTOR CHANNEL THROUGH THE...
- Publication number 20210257492
- Publication date Aug 19, 2021
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20210167209
- Publication date Jun 3, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20210167210
- Publication date Jun 3, 2021
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS
- Publication number 20200411640
- Publication date Dec 31, 2020
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH CHANNEL AND SUB-CHANNEL REGIONS WITH DISTINCT COMP...
- Publication number 20200411513
- Publication date Dec 31, 2020
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS
- Publication number 20200220014
- Publication date Jul 9, 2020
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION...
- Publication number 20200219975
- Publication date Jul 9, 2020
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN ST...
- Publication number 20200105759
- Publication date Apr 2, 2020
- Intel Corporation
- Anupama BOWONDER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH CONTACT ETCH STOP LAYER
- Publication number 20200006504
- Publication date Jan 2, 2020
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED ETCH-STOP LAYER TO HELP CONTROL TRANSISTOR SOURCE/DRAIN DEPTH
- Publication number 20200006488
- Publication date Jan 2, 2020
- Intel Corporation
- RISHABH MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL STRUCTURES WITH SUB-FIN DOPANT DIFFUSION BLOCKING LAYERS
- Publication number 20200006332
- Publication date Jan 2, 2020
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE EDGE ARCHITECTURE WITH ALTERNATE CHANNEL MATERIAL
- Publication number 20200006487
- Publication date Jan 2, 2020
- Intel IP Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH RELATIVELY HIGH GERMANIUM CONTENT
- Publication number 20200006491
- Publication date Jan 2, 2020
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR LAYER BETWEEN SOURCE/DRAIN REGIONS AND GATE SPACERS
- Publication number 20190355811
- Publication date Nov 21, 2019
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND...
- Publication number 20190326290
- Publication date Oct 24, 2019
- Intel Corporation
- STEPHEN M. CEA
- H01 - BASIC ELECTRIC ELEMENTS

Anupama Bowonder

Person

Patents Grantslast 30 patents

Fin smoothing and integrated circuit structures resulting therefrom

Channel structures with sub-fin dopant diffusion blocking layers

Sub-fin leakage reduction for template strained materials

Fin shaping and integrated circuit structures resulting therefrom

Epitaxial oxide plug for strained transistors

Integrated circuit structures with source or drain dopant diffusion...

Fin smoothing and integrated circuit structures resulting therefrom

Sub-fin leakage reduction for template strained materials

Channel structures with sub-fin dopant diffusion blocking layers

Multiple strain states in epitaxial transistor channel through the...

Integrated circuit structures having asymmetric source and drain st...

Self-aligned gate edge architecture with alternate channel material

Buried etch-stop layer to help control transistor source/drain depth

Source or drain structures with contact etch stop layer

Epitaxial oxide plug for strained transistors

Semiconductor layer between source/drain regions and gate spacers

Transistors with channel and sub-channel regions with distinct comp...

Techniques for forming dual-strain fins for co-integrated n-MOS and...

Tunneling transistor suitable for low voltage operation

Tunneling transistor suitable for low voltage operation

Patents Applicationslast 30 patents

MODULATION OF CHIP PERFORMANCE BY CONTROLLING TRANSISTOR GATE PROFILE

FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

GATE CUT, AND SOURCE AND DRAIN CONTACTS

METAL GATE CUT WITH HYBRID MATERIAL FILL

MOBILITY IMPROVEMENT IN GATE ALL AROUND TRANSISTORS BASED ON SUBSTR...

INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION...

FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

TRANSISTORS WITH EPITAXIAL SOURCE/DRAIN LINER FOR IMPROVED CONTACT...

SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS

FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

CHANNEL STRUCTURES WITH SUB-FIN DOPANT DIFFUSION BLOCKING LAYERS

REDUCED CONTACT RESISTIVITY WITH PMOS GERMANIUM AND SILICON DOPED W...

EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS

MULTIPLE STRAIN STATES IN EPITAXIAL TRANSISTOR CHANNEL THROUGH THE...

FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS

TRANSISTORS WITH CHANNEL AND SUB-CHANNEL REGIONS WITH DISTINCT COMP...

EPITAXIAL OXIDE PLUG FOR STRAINED TRANSISTORS

INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN DOPANT DIFFUSION...

INTEGRATED CIRCUIT STRUCTURES HAVING ASYMMETRIC SOURCE AND DRAIN ST...

SOURCE OR DRAIN STRUCTURES WITH CONTACT ETCH STOP LAYER

BURIED ETCH-STOP LAYER TO HELP CONTROL TRANSISTOR SOURCE/DRAIN DEPTH

CHANNEL STRUCTURES WITH SUB-FIN DOPANT DIFFUSION BLOCKING LAYERS

SELF-ALIGNED GATE EDGE ARCHITECTURE WITH ALTERNATE CHANNEL MATERIAL

SOURCE OR DRAIN STRUCTURES WITH RELATIVELY HIGH GERMANIUM CONTENT

SEMICONDUCTOR LAYER BETWEEN SOURCE/DRAIN REGIONS AND GATE SPACERS

TECHNIQUES FOR FORMING DUAL-STRAIN FINS FOR CO-INTEGRATED N-MOS AND...