Patent Application
20240213100
The present disclosure relates to integrated circuits, and more particularly, to metal gate cuts made in semiconductor devices.
As integrated circuits continue to scale downward in size, a number of challenges arise. For instance, reducing the size of memory and logic cells is becoming increasingly more difficult, as is reducing device spacing at the device layer. As transistors are packed more densely, the formation of certain device structures used to isolate adjacent transistors becomes challenging. Accordingly, there remain a number of non-trivial challenges with respect to forming semiconductor devices.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used.
Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to device layer transistors, such as finFETs or gate-all-around transistors (e.g., ribbonFETs and nanowire FETs). In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends from a source region to a drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from a source region to a drain region. The gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal). The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a hybrid structure having both a relatively low-k dielectric material and a relatively high-k dielectric material. In one such example case, the gate cut includes a liner or outer layer of a high-k dielectric material and a low-k dielectric fill material on that liner or outer layer. The inclusion of low-k dielectric fill material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut. In some cases, the gate cut further includes a capping layer of high-k dielectric material on the low-k dielectric fill material. The high-k dielectric material of the capping layer may be the same as the liner or outer layer, but need not be. In any such cases, the dielectric constant(s) of the liner or outer layer and capping layer (if present) is/are higher than the dielectric constant of the fill material. Numerous variations and embodiments will be apparent in light of this disclosure.
As previously noted above, there remain a number of non-trivial challenges with respect to integrated circuit fabrication. In more detail, as devices become smaller and more densely packed, many structures become more challenging to fabricate as critical dimensions (CD) of the structures push the limits of current fabrication technology. Example structures like gate cuts are used in integrated circuit design to isolate gate structures from one another. Such gate cuts may be relatively thin and are thus filled with a robust high-k dielectric material (e.g., a material with a dielectric constant of 6.5 or greater, such as silicon nitride). But this can lead to high parasitic capacitance between the conductive gate electrode on either side of the gate cut. Using a low-k dielectric material to fill a gate cut structure can help to reduce such parasitic capacitance. However, low-k materials usually include an oxygen component, and deposition of oxygen-containing dielectric materials implicates oxidation risk of the underlying material(s). Also, deposition of oxygen-containing dielectric materials includes ion flux. Such factors can cause shifting in electrical properties of the underlying material(s). Also, oxygen-rich low-k dielectric materials may not be robust enough to withstand erosion caused by, for example, downstream processing and planarization.
Thus, and in accordance with an embodiment of the present disclosure, techniques are provided herein to form gate cuts through a metal gate structure that include a hybrid material structure, which incorporates both high-k and low-k materials. In some embodiments, a metal gate cut includes an outer layer along edges of the metal gate cut that includes a high-k material (e.g., material with a dielectric constant greater than or equal to 6.5). The outer layer may include, for example, a conformal deposition of silicon nitride or other suitable relatively high-k material. Since the outer layer is along the edges of the gate cut, it may contact the gate electrode on either side of the gate cut. The metal gate cut also includes a dielectric fill on the outer layer and within an inner portion of the gate cut. According to some embodiments, the dielectric fill includes a low-k material (e.g., material with a dielectric constant less than or equal to 4.5). Silicon dioxide or flowable silicon dioxide or porous silicon dioxide may be used for the dielectric fill, to provide a few examples. In some embodiments, the gate cut also includes a dielectric cap over the dielectric fill to protect the dielectric fill from subsequent processing. The dielectric cap may include a high-k material, and in some examples, is the same material as the outer layer of the gate cut.
Using the hybrid material profile for the gate cut can cause a 2-3% performance gain over gate cuts that use only high-k materials, due to the decrease in the parasitic capacitance. Additionally, the techniques described herein allow for a gate cut configuration that further includes a conductive via passing through the hybrid gate cut structure, thus allowing for contact to backside structures. The hybrid material scheme for the gate cut, which incorporates both high-k and low-k materials provides for a robust structure that can both withstand downstream processing and reduce the parasitic capacitance between the conductive via and the gate electrode adjacent to the gate cut.
According to an embodiment, an integrated circuit includes a first semiconductor device having a first semiconductor region extending in a first direction from a first source region to a first drain region, and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction from a second source region to a second drain region, and a second gate structure extending in the second direction over the second semiconductor region, and a gate cut between the first gate structure and the second gate structure. The gate cut includes a first dielectric layer along edges of the gate cut, a dielectric fill on the first dielectric layer, and a second dielectric layer on a top surface of the dielectric fill. The first and second dielectric layers each has a higher dielectric constant than the dielectric fill.
According to an embodiment, an integrated circuit includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions, a gate structure extending in a second direction over the one or more semiconductor regions, and a gate cut extending in a third direction through an entire thickness of the gate structure. The gate cut includes a first dielectric layer along edges of the gate cut, a second dielectric layer on the first dielectric layer, a third dielectric layer on a top surface of the second dielectric layer, and a conductive contact extending through a central axis of the gate cut and along an entire height of at least the second dielectric layer in the third direction. The second dielectric layer has a lower dielectric constant than each of the first and third dielectric layers.
According to another embodiment, a method of forming an integrated circuit includes forming a first fin comprising first semiconductor material and a second fin comprising second semiconductor material, the first and second fins extending above a substrate and each extending in a first direction; forming a gate electrode extending over the first semiconductor material and the second semiconductor material in a second direction different from the first direction; forming a recess through an entire thickness of the gate electrode between the first fin and the second fin; forming a first dielectric layer within the recess; forming a dielectric fill within a remaining volume of the recess and on the first dielectric layer, wherein the first dielectric layer has a higher dielectric constant than the dielectric fill; recessing a top surface of the dielectric fill; and forming a second dielectric layer on the top surface of the dielectric fill.
The techniques can be used with any type of non-planar transistors, including finFETs (sometimes called tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or forksheet transistors, to name a few examples. The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions that are deposited during an etch-and-replace source/drain forming process. The dopant-type in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate, or RMG, process). Any number of semiconductor materials can be used in forming the transistors, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For instance, in some example embodiments, such tools may indicate the presence of different dielectric materials making up a gate cut, and specifically, both low-k and high-k dielectric materials. In some embodiments, such tools may indicate a high-k material conformal to or otherwise along edges of a gate cut, and a low-k fill material within the inner portion of the gate cut and on the high-k material. In some such embodiments, the gate cut may further include a high-k capping layer and/or a conductive via extending through the gate cut. Numerous configurations and variations will be apparent in light of this disclosure.
It should be readily understood that the meaning of “above” and “over” in the present disclosure should be interpreted in the broadest manner such that “above” and “over” not only mean “directly on” something but also include the meaning of over something with an intermediate feature or a layer therebetween. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A monolayer is a layer that consists of a single layer of atoms of a given material. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A layer can be conformal to a given surface (whether flat or curvilinear) with a relatively uniform thickness across the entire layer.
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not in the other material.
As can be seen, semiconductor devices 101 and 103 are formed on a substrate 102. Any number of semiconductor devices can be formed on substrate 102, but two are used here as an example. Substrate 102 can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some example embodiments, a lower portion of (or all of) substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing.
Each of semiconductor devices 101 and 103 includes one or more nanoribbons 104 that extend parallel to one another along a direction between a source region and a drain region (e.g., a first direction into and out of the page in the cross-section view of
As can further be seen, adjacent semiconductor devices are separated by a dielectric fill 106 that may include silicon dioxide. Dielectric fill 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices, and adjacent subfin regions 108. Dielectric fill 106 can be any suitable dielectric material, such as silicon dioxide, aluminum oxide, or silicon oxycarbonitride.
Semiconductor devices 101 and 103 each include a subfin region 108, in this example. According to some embodiments, subfin region 108 comprises the same semiconductor material as substrate 102 and is adjacent to dielectric fill 106. According to some embodiments, nanoribbons 104 (or other semiconductor bodies) extend between a source and a drain region in the first direction to provide an active region for a transistor (e.g., the semiconductor region beneath the gate). The source and drain regions are not shown in the cross-section of
According to some embodiments, the source and drain regions are epitaxial regions that are provided using an etch-and-replace process. In other embodiments one or both of the source and drain regions could be, for example, implantation-doped native portions of the semiconductor fins or substrate. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials). The source and drain regions may include multiple layers such as liners and capping layers to improve contact resistance. In any such cases, the composition and doping of the source and drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one transistor is a p-type MOS (PMOS) transistor, and the other transistor is an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used.
According to some embodiments, a first gate structure extends over nanoribbons 104 of semiconductor device 101 along a second direction across the page while a second gate structure extends over nanoribbons 104 of semiconductor device 103 along the second direction. The second direction may be orthogonal to the first direction. Each gate structure includes a respective gate dielectric 116a/116b and a gate layer (or gate electrode) 118a/118b. Gate dielectric 116a/116b represents any number of dielectric layers present between nanoribbons 104 and gate layer 118a/118b. Gate dielectric 116a/116b may also be present on the surfaces of other structures within the gate trench, such as on subfin region 108. Gate dielectric 116a/116b may include any suitable gate dielectric material(s). In some embodiments, gate dielectric 116a/116b includes a layer of native oxide material (e.g., silicon dioxide) on the nanoribbons or other semiconductor regions making up the channel region of the devices, and a layer of high-K dielectric material (e.g., hafnium oxide) on the native oxide.
Gate layer 118a/118b may represent any number of conductive layers, such as any metal, metal alloy, or doped polysilicon layers. In some embodiments, gate layer 118a/118b includes one or more workfunction metals around nanoribbons 104. In some embodiments, one of semiconductor devices 101 and 103 is a p-channel device that include a workfunction metal having titanium around its nanoribbons 104 and the other semiconductor device is an n-channel device that includes a workfunction metal having tungsten around its nanoribbons 104. Gate layer 118a/118b may also include a fill metal or other conductive material (e.g., tungsten, ruthenium, molybdenum, copper, aluminum) around the workfunction metals to provide the whole gate electrode structure. In some embodiments, a gate cap 119 may be formed over gate electrode 118a/118b to protect the underlying material during processing. Gate cap 119 may be any suitable dielectric material, such as silicon nitride.
According to some embodiments, adjacent gate structures may be separated along the second direction (e.g., across the page) by a gate cut 120, which acts like a dielectric barrier or wall between gate structures. Gate cut 120 extends vertically (e.g., in a third direction) through at least an entire thickness of the adjacent gate structure. In some embodiments, gate cut 120 also extends through an entire thickness of dielectric fill 106. According to some embodiments, gate cut 120 is formed from various dielectric materials to form a hybrid material structure. For example, gate cut 120 includes a first dielectric layer 122 along an outer edge of gate cut 120 and a dielectric fill 124 on first dielectric layer 122 and within an inner portion of gate cut 120. According to some embodiments, first dielectric layer 122 includes a high-k dielectric material, such as silicon nitride or aluminum oxide, and dielectric fill 124 includes a low-k dielectric material, such as silicon dioxide, porous silicon dioxide, or flowable oxide. First dielectric layer 122 may be conformal and have a thickness between about 2 nm and about 4 nm. According to some embodiments, dielectric fill 124 does not extend to the top surface of gate cut 120 due to the presence of a dielectric cap 126 on dielectric fill 124. Dielectric cap 126 may include a high-k dielectric material and may be the same high-k dielectric material as first dielectric layer 122, but need not be the same. In some examples, dielectric cap 126 has a thickness between about 20 nm and about 30 nm. In some examples, dielectric cap includes silicon nitride or silicon carbide. Gate cut 120 may have a top width along the second direction between about 40 nm and about 50 nm. Other examples may not include dielectric cap 126, thus leaving the dielectric fill 124 co-planar with the top of the structure.
Gate cut 120 also extends in the first direction as seen in
According to some embodiments, sacrificial layers 202 have a different material composition than semiconductor layers 204. In some embodiments, sacrificial layers 202 are silicon germanium (SiGe) while semiconductor layers 204 include a semiconductor material suitable for use as a nanoribbon such as silicon (Si), SiGe, germanium, or III-V materials like indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layers 202 and in semiconductor layers 204, the germanium concentration is different between sacrificial layers 202 and semiconductor layers 204. For example, sacrificial layers 202 may include a higher germanium content compared to semiconductor layers 204. In some examples, semiconductor layers 204 may be doped with either n-type dopants (to produce a p-channel transistor) or p-type dopants (to produce an n-channel transistor).
While dimensions can vary from one example embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each of semiconductor layers 204 may be about the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of sacrificial layers 202 and semiconductor layers 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
According to some embodiments, an anisotropic etching process through the layer stack continues into at least a portion of substrate 201. The etched portion of substrate 201 may be filled with a dielectric fill 206 that acts as shallow trench isolation (STI) between adjacent fins. Dielectric fill 206 may be any suitable dielectric material such as silicon dioxide. Subfin regions 208 represent remaining portions of substrate 201 between dielectric fill 206, according to some embodiments.
Following the formation of sacrificial gate 210 (and prior to replacement of sacrificial gate 210 with a metal gate), additional semiconductor device structures are formed that are not shown in these cross-sections. These additional structures include spacer structures on the sidewalls of sacrificial gate 210 and source and drain regions on either ends of each of the fins. The formation of such structures can be accomplished using any number of processing techniques.
In the example where the fins include alternating semiconductor layers, sacrificial layers 202 are selectively removed to release nanoribbons 212 that extend between corresponding source or drain regions. Each vertical set of nanoribbons 212 represents the semiconductor or channel region of a different semiconductor device. It should be understood that nanoribbons 212 may also be nanowires or nanosheets (e.g., from a forksheet arrangement) or fins (e.g., for a finFET arrangement). Sacrificial gate 210 and sacrificial layers 202 may be removed using the same isotropic etching process or different isotropic etching processes.
As noted above, gate electrode 216 can represent any number of conductive layers. The conductive gate electrode 216 may be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples. In some embodiments, gate electrode 216 includes doped polysilicon, a metal, or a metal alloy. Example suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and carbides and nitrides thereof. Gate electrode 216 may include, for instance, a metal fill material along with one or more workfunction layers, resistance-reducing layers, and/or barrier layers. The workfunction layers can include, for example, p-type workfunction materials (e.g., titanium nitride) for PMOS gates, or n-type workfunction materials (e.g., titanium aluminum carbide) for NMOS gates. Following the formation of the gate structure, the entire structure may be polished or planarized such that the top surface of the gate structure (e.g., top surface of gate electrode 216) is planar with the top surface of other semiconductor elements, such as the spacer structures that define the gate trench.
Masking structure 218 may include any number of hard mask layers, such as any dielectric layers or carbon hard mask layers. An opening 220 may be formed through masking structure 218 and gate cap 217 to expose a portion of gate electrode 216 where a gate cut will be formed. A reactive ion etching (RIE) process may be used to form opening 220, according to some examples.
Dielectric fill 226 may overflow out of gate cut recess 222 and be polished back using chemical mechanical polishing (CMP), according to some embodiments. In the illustrated example, dielectric fill 226 is polished back to be substantially level with a top surface of first dielectric layer 224. In other examples, dielectric fill 226 may be polished back to be substantially level with a top surface of masking structure 218 or a top surface of gate cap 217.
Conductive via 302 may be provided to contact backside structures formed during subsequent processing. For example, in some embodiments, substrate 201 may be removed from the backside (e.g., via a CMP process), thus exposing a bottom surface of conductive via 302. A backside layer of dielectric material (e.g., silicon dioxide) may then be deposited, and one or more conductive structures may then be formed in that dielectric layer on the backside and contacting conductive via 302. The presence of dielectric fill 226 with its low-k dielectric material helps to reduce parasitic capacitance between conductive via 302 and gate electrode 216.
As can be further seen, chip package 400 includes a housing 404 that is bonded to a package substrate 406. The housing 404 may be any standard or proprietary housing, and may provide, for example, electromagnetic shielding and environmental protection for the components of chip package 400. The one or more dies 402 may be conductively coupled to a package substrate 406 using connections 408, which may be implemented with any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid array (BGA), pins, or wire bonds, to name a few examples. Package substrate 406 may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between the faces of package substrate 406, or between different locations on each face. In some embodiments, package substrate 406 may have a thickness less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of package geometries can be used. Additional conductive contacts 412 may be disposed at an opposite face of package substrate 406 for conductively contacting, for instance, a printed circuit board (PCB). One or more vias 410 extend through a thickness of package substrate 406 to provide conductive pathways between one or more of connections 408 to one or more of contacts 412. Vias 410 are illustrated as single straight columns through package substrate 406 for ease of illustration, although other configurations can be used (e.g., damascene, dual damascene, through-silicon via, or an interconnect structure that meanders through the thickness of substrate 406 to contact one or more intermediate locations therein). In still other embodiments, vias 410 are fabricated by multiple smaller stacked vias, or are staggered at different locations across package substrate 406. In the illustrated embodiment, contacts 412 are solder balls (e.g., for bump-based connections or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). In some embodiments, a solder resist is disposed between contacts 412, to inhibit shorting.
In some embodiments, a mold material 414 may be disposed around the one or more dies 402 included within housing 404 (e.g., between dies 402 and package substrate 406 as an underfill material, as well as between dies 402 and housing 404 as an overfill material). Although the dimensions and qualities of the mold material 414 can vary from one embodiment to the next, in some embodiments, a thickness of mold material 414 is less than 1 millimeter. Example materials that may be used for mold material 414 include epoxy mold materials, as suitable. In some cases, the mold material 414 is thermally conductive, in addition to being electrically insulating.
Method 500 begins with operation 502 where any number of parallel semiconductor fins are formed, according to some embodiments. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed of material deposited onto an underlying substrate. In one such example case, a blanket layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In another such example, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitates forming of nanowires and nanoribbons during a gate forming process where one type of the alternating layers are selectively etched away so as to liberate the other type of alternating layers within the channel region, so that a gate-all-around (GAA) process can then be carried out. The alternating layers can be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins may also include a cap structure over each fin that is used to define the locations of the fins during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.
According to some embodiments, a dielectric layer is formed around subfin portions of the one or more fins. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and runs lengthwise in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate and the dielectric layer may be formed within the recessed portions of the substrate. Accordingly, the dielectric layer acts as shallow trench isolation (STI) between adjacent fins. The dielectric layer may be any suitable dielectric material, such as silicon dioxide.
Method 500 continues with operation 504 where a sacrificial gate and spacer structures are formed over the fins. The sacrificial gate may be patterned using a gate masking layer in a strip that runs orthogonally over the fins (many gate masking layers and corresponding sacrificial gates may be formed parallel to one another (e.g., forming a cross-hatch pattern with the fins). The gate masking layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed from any suitable material that can be selectively removed at a later time without damaging the semiconductor material of the fins. In one example, the sacrificial gate includes polysilicon. The spacer structures may be deposited and then etched back such that the spacer structures remain mostly only on sidewalls of any exposed structures. According to some embodiments, the spacer structures may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.
Method 500 continues with operation 506 where source or drain regions are formed at the ends of the semiconductor regions of each of the fins. Any portions of the fins not protected by the sacrificial gate and spacer structures may be removed using, for example, an anisotropic etching process followed by the epitaxial growth of the source or drain regions from the exposed ends of the semiconductor layers in the fins. In some example embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe). Another dielectric fill may be formed adjacent to the various source or drain regions for additional electrical isolation between adjacent regions. The dielectric fill may also extend over a top surface of the source or drain regions. In some embodiments, topside conductive contacts may be formed through the dielectric fill to contact one or more of the source or drain regions.
Method 500 continues with operation 508 where the sacrificial gate is removed and replaced with a gate structure. The sacrificial gate may be removed using an isotropic etching process that selectively removes all of the material from the sacrificial gate, thus exposing the various fins between the set of spacer structures. In the example case where GAA transistors are used, any sacrificial layers within the exposed fins between the spacer structures may also be removed to release nanoribbons, nanosheets, or nanowires of semiconductor material.
The gate structure may include both a gate dielectric and a gate electrode. The gate dielectric is first formed over the exposed semiconductor regions between the spacer structures followed by forming the gate electrode within the remainder of the trench between the spacer structures, according to some embodiments. The gate dielectric may include any number of dielectric layers deposited using a CVD process, such as ALD. The gate electrode can include any number of conductive material layers, such as any metals, metal alloys, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples. In some embodiments, the gate electrode may be recessed, and a dielectric gate cap is formed within the recessed area. The dielectric gate cap may have a thickness between 10 nm and 20 nm, such as around 15 nm.
Method 500 continues with operation 510 where a deep recess is formed through an entire thickness of the gate structure. A mask structure may be formed over the gate structure and an opening may be formed through the mask structure to expose a portion of the underlying gate electrode. According to some embodiments, the opening through the mask structure is at a location where the deep recess is to be formed through the underlying gate electrode. The mask structure may include any number of hard mask layers, such as any dielectric layers or carbon hard mask layers. The opening may be formed using a directional RIE process. According to some embodiments, the deep recess has a high height-to-width aspect ratio of at least 6:1 and extends through at least an entire thickness of the gate structure. In some examples, the deep recess also extends through an entire thickness of the dielectric fill between devices and into the underlying substrate.
Method 500 continues with operation 512 where a first dielectric layer is formed within the recess and on the exposed sidewalls of the gate electrode. According to some embodiments, the first dielectric layer includes a high-k dielectric material, such as silicon nitride or silicon carbide or any other material having a dielectric constant of at least 6.5. The first dielectric layer may be deposited using ALD to a thickness between about 2 nm and about 4 nm.
Method 500 continues with operation 514 where a dielectric fill is formed within the recess and on the first dielectric layer. According to some embodiments, the dielectric fill includes a low-k dielectric material, such as silicon dioxide or flowable oxide or any other material having a dielectric constant of at most 4.5. The dielectric fill may be polished back until a top surface of the dielectric fill is level with a top surface of the mask structure or with a top surface of the dielectric gate cap on the gate electrode. In some examples, the dielectric fill is flowable silicon dioxide and the first dielectric layer is silicon nitride.
Method 500 continues with operation 516 where the dielectric fill is recessed. The dielectric fill may be recessed via any number of wet or dry etching processes. In some examples, a top surface of the dielectric fill is recessed such that it at least falls below a top surface of the gate electrode. In some embodiments, the top surface of the dielectric fill is recessed such that it is between 15 nm and 25 below the top surface of the gate electrode. Some examples may not recess the dielectric fill, thus leaving the dielectric fill co-planar with the top of the structure (e.g., such as shown in
Method 500 continues with operation 518 where a second dielectric layer is formed on a top surface of the dielectric fill. The second dielectric layer may include a high-k dielectric material, such as the same material as the first dielectric layer. The second dielectric layer may be deposited such that it substantially fills the recessed area previously occupied by the dielectric fill. Following deposition, the second dielectric layer may be polished back using CMP until a top surface of the second dielectric layer is substantially coplanar with a top surface of the dielectric gate cap over the gate electrode. The second dielectric layer can form a cap structure over the dielectric fill, such that the dielectric fill is fully encapsulated by the first dielectric layer and the second dielectric layer.
Depending on its applications, computing system 600 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 600 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment, such as a module including an integrated circuit on a substrate, the substrate having semiconductor devices and at least one gate cut having a hybrid material structure (e.g., having both low-k and high-k dielectric materials). In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 606 can be part of or otherwise integrated into the processor 604).
The communication chip 606 enables wireless communications for the transfer of data to and from the computing system 600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 606 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 600 may include a plurality of communication chips 606. For instance, a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more semiconductor devices as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 606 also may include an integrated circuit die packaged within the communication chip 606. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 604 (e.g., where functionality of any chips 606 is integrated into processor 604, rather than having separate communication chips). Further note that processor 604 may be a chip set having such wireless capability. In short, any number of processor 604 and/or communication chips 606 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 600 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
It will be appreciated that in some embodiments, the various components of the computing system 600 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components or any suitable combination of hardware, firmware or software.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1 is an integrated circuit that includes a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the second semiconductor region, and a gate cut between the first gate structure and the second gate structure. The gate cut includes a first dielectric layer along edges of the gate cut, a dielectric fill on the first dielectric layer, and a second dielectric layer on a top surface of the dielectric fill. The first dielectric layer has a higher dielectric constant than the dielectric fill.
Example 2 includes the integrated circuit of Example 1, wherein the first dielectric layer directly contacts the first gate structure and the second gate structure.
Example 3 includes the integrated circuit of Example 1 or 2, wherein the first dielectric layer comprises silicon and nitrogen.
Example 4 includes the integrated circuit of any one of Examples 1-3, wherein the first dielectric layer has a thickness between about 2 nm and about 4 nm.
Example 5 includes the integrated circuit of any one of Examples 1-4, wherein the dielectric fill comprises silicon and oxygen.
Example 6 includes the integrated circuit of any one of Examples 1-5, wherein the second dielectric layer comprises silicon and nitrogen or comprises silicon and carbon.
Example 7 includes the integrated circuit of any one of Examples 1-6, wherein the second dielectric layer has a thickness between about 20 nm and about 30 nm.
Example 8 includes the integrated circuit of any one of Examples 1-7, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons.
Example 9 includes the integrated circuit of Example 8, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.
Example 10 includes the integrated circuit of any one of Examples 1-9, wherein the first gate structure includes a first gate dielectric around the first semiconductor region, and the second gate structure includes a second gate dielectric around the second semiconductor region.
Example 11 includes the integrated circuit of Example 10, wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
Example 12 includes the integrated circuit of any one of Examples 1-11, wherein the gate cut further comprises a conductive via extending vertically in a third direction through the gate cut.
Example 13 is a printed circuit board having the integrated circuit of any one of Examples 1-12.
Example 14 is an electronic device that includes a chip package having one or more dies. At least one of the one or more dies includes a first semiconductor device having a first semiconductor region extending in a first direction between a first source region and a first drain region, and a first gate structure extending in a second direction over the first semiconductor region, a second semiconductor device having a second semiconductor region extending in the first direction between a second source region and a second drain region, and a second gate structure extending in the second direction over the second semiconductor region, and a gate cut between the first gate structure and the second gate structure. The gate cut includes a first dielectric layer along edges of the gate cut, a dielectric fill on the first dielectric layer, and a second dielectric layer on a top surface of the dielectric fill. The first dielectric layer has a higher dielectric constant than the dielectric fill.
Example 15 includes the electronic device of Example 14, wherein the first dielectric layer directly contacts the first gate structure and the second gate structure.
Example 16 includes the electronic device of Example 14 or 15, wherein the first dielectric layer comprises silicon and nitrogen.
Example 17 includes the electronic device of any one of Examples 14-16, wherein the first dielectric layer has a thickness between about 2 nm and about 4 nm.
Example 18 includes the electronic device of any one of Examples 14-17, wherein the dielectric fill comprises silicon and oxygen.
Example 19 includes the electronic device of any one of Examples 14-18, wherein the second dielectric layer comprises silicon and nitrogen or comprises silicon and carbon.
Example 20 includes the electronic device of any one of Examples 14-19, wherein the second dielectric layer has a thickness between about 20 nm and about 30 nm.
Example 21 includes the electronic device of any one of Examples 14-20, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons and the second semiconductor region comprises a plurality of second semiconductor nanoribbons.
Example 22 includes the electronic device of Example 21, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons comprise germanium, silicon, or a combination thereof.
Example 23 includes the electronic device of any one of Examples 14-22, wherein the first gate structure includes a first gate dielectric around the first semiconductor region, and the second gate structure includes a second gate dielectric around the second semiconductor region.
Example 24 includes the electronic device of Example 23, wherein the first gate dielectric and the second gate dielectric are not present on any sidewall of the gate cut.
Example 25 includes the electronic device of any one of Examples 14-24, wherein the gate cut further comprises a conductive via extending vertically in a third direction through the gate cut.
Example 26 includes the electronic device of any one of Examples 14-25, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.
Example 27 is a method of forming an integrated circuit. The method includes forming a first fin comprising first semiconductor material and a second fin comprising second semiconductor material, the first and second fins extending above a substrate and each extending in a first direction; forming a gate electrode extending over the first semiconductor material and the second semiconductor material in a second direction different from the first direction; forming a recess through an entire thickness of the gate electrode between the first fin and the second fin; forming a first dielectric layer within the recess; forming a dielectric fill within a remaining volume of the recess and on the first dielectric layer, wherein the first dielectric layer has a higher dielectric constant than the dielectric fill; recessing a top surface of the dielectric fill; and forming a second dielectric layer on the top surface of the dielectric fill.
Example 28 includes the method of Example 27, further comprising forming an additional recess through an entire thickness of at least the dielectric fill; forming a dielectric liner within the additional recess; and forming a conductive fill within a remaining volume of the additional recess and on the dielectric liner.
Example 29 includes the method of Example 27 or 28, further comprising forming source and drain regions at ends of the first semiconductor material and the second semiconductor material.
Example 30 includes the method of any one of Examples 27-29, further comprising polishing a top surface of the second dielectric layer using chemical mechanical polishing (CMP).
Example 31 is an integrated circuit that includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions, a gate structure extending in a second direction over the one or more semiconductor regions, and a gate cut extending in a third direction through an entire thickness of the gate structure. The gate cut includes a first dielectric layer along edges of the gate cut, a second dielectric layer on the first dielectric layer, a third dielectric layer on a top surface of the second dielectric layer, and a conductive via extending through a central axis of the gate cut and along an entire height of at least the second dielectric layer in the third direction. The second dielectric layer has a lower dielectric constant than the first dielectric layer.
Example 32 includes the integrated circuit of Example 31, wherein the first dielectric layer directly contacts the gate structure.
Example 33 includes the integrated circuit of Example 31 or 32, wherein the first dielectric layer comprises silicon and nitrogen.
Example 34 includes the integrated circuit of any one of Examples 31-33, wherein the first dielectric layer has a thickness between about 2 nm and about 4 nm.
Example 35 includes the integrated circuit of any one of Examples 31-34, wherein the second dielectric layer comprises silicon and oxygen.
Example 36 includes the integrated circuit of any one of Examples 31-35, wherein the third dielectric layer comprises silicon and nitrogen or comprises silicon and carbon.
Example 37 includes the integrated circuit of any one of Examples 31-36, wherein the third dielectric layer has a thickness between about 20 nm and about 30 nm.
Example 38 includes the integrated circuit of any one of Examples 31-37, wherein the gate structure includes a gate dielectric around the one or more semiconductor regions, and wherein the gate dielectric is not present on any sidewall of the gate cut.
Example 39 is a printed circuit board having the integrated circuit of any one of Examples 31-38.
The foregoing description of the embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but rather by the claims appended hereto.
