Patent Application
20240222447
The present disclosure relates to integrated circuits, and more particularly, to source or drain contacts of transistor devices.
As integrated circuits continue to scale downward in size, a number of challenges arise. For example, as transistors are packed more densely in a given device layer, the interconnection and routing of devices, as well as achieving low contact resistance, becomes challenging. Accordingly, there remain a number of non-trivial challenges with respect to forming semiconductor devices.
FIG. 3C2 illustrates an example plan view of the structure of
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For instance, while some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and/or rounded corners), and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. Likewise, while the thickness of a given first layer may appear to be similar in thickness to a second layer, in actuality that first layer may be much thinner or thicker than the second layer; same goes for other layer or feature dimensions.
Techniques are described herein for providing source and drain contacts in transistor devices. In some examples, a continuous and monolithic contact is initially formed on neighboring source or drain regions, and a gate cut is then formed to bifurcate that monolithic contact into two separate contacts. In some such cases, the bifurcated contacts may be conjoined or otherwise reconnected by an overlying bridge conductor or other interconnect feature(s). By initially forming a larger continuous and monolithic contact over multiple source or drain regions, a higher quality contact may be made to each underlying source or drain region. Then, a gate cut can be used to break contact in locations where desired. Also, a bridging contact can be subsequently added to reconnect any contacts that actually should be connected. Numerous configurations and variations will be apparent in light of this disclosure.
As previously noted above, routing signals and/or power to and/or from individual transistors has become even more challenging, due to diminishing device sizes. For example, the spacing available for source and drain contacts is getting smaller and smaller, due to further scaling of the diffusion regions. As such, contact resistance is becoming a more and more challenging issue.
Thus, and in accordance with an embodiment of the present disclosure, techniques are described herein for forming source and drain contacts in transistor devices. In some examples, a continuous and monolithic contact is initially formed on neighboring source or drain (diffusion) regions. The contact deposition may deposit on top and side surfaces of one or more of the diffusion regions. Subsequently, the continuous and monolithic contact is divided into two or more separate contacts, by forming one or more corresponding gate cuts that pass through the continuous and monolithic contact. Each such gate cut also passes between neighboring diffusion regions. In some such cases, an overlying bridge contact may be provided to reconnect diffusion contacts that are severed during a gate cut process. In this sense, the techniques provided herein can be used to opportunistically use the gate cut process to reduce contact resistance between a source or drain contact and a corresponding source or drain region. Note that the gate cut is formed after the diffusion contacts are provided. Thus, some depositions attributable to the diffusion contact process may not be on the gate cut. For instance, some diffusion contacts may include a liner or barrier layer that is deposited prior to deposition of a conductive fill material. In such cases, the liner or barrier layer will not extend along the gate cut sidewall as it would otherwise do if the gate cut structure was present when the contact trench was formed and the liner or barrier layer was deposited.
In an example, assume a first device laterally adjacent to a second device, and a first source or drain region of the first device is laterally adjacent to a second source or drain region of the second device. The first and second devices may be, for example, metal oxide semiconductor (MOS) transistors (e.g., non-planar MOS transistors), such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. Thus, the channel regions of individual devices may comprise nanoribbons, nanowires, nanosheets, or a fin-based structure. Initially (e.g., prior to formation of the gate cut) a monolithic and continuous source or drain contact structure may be in contact with both the first and second source or drain regions. For example, the continuous source or drain contact structure is above the first source or drain region and the second source or drain region. Similarly, a continuous gate structure may be provided initially for both the first and second devices.
In one such embodiment, subsequently, during a gate cut formation process, a gate cut comprising dielectric material is formed, and which extends through the continuous gate structure, to provide two separate gate structures for the two corresponding devices. However, in an example, the gate cut process is non-selective, and the gate cut thus also extends though the continuous source or drain contact structure, to bifurcate the continuous source or drain contact structure into (i) a first source or drain contact for the first device, and (ii) a second source or drain contact for the second device.
In some such examples, the design of the circuit may, however, dictate that the first and second source or drain contacts be electrically coupled. Accordingly, a bridge contact may be subsequently formed, which laterally extends from an upper surface of the first source or drain contact to an upper surface of the second source or drain contact, thereby reconnecting or otherwise coupling the two source or drain contacts. The bridge contact extends above the dielectric material of the gate cut.
In some such examples, the source or drain contact may be only on an upper surface, but not be on sidewalls, of the corresponding source or drain region. This may help to increase a lateral gap between adjacent source or drain contacts, e.g., to reduce chances of electrical shorting between adjacent contacts. However, in other examples, the initially formed continuous source or drain contact structure can be on one or more sidewalls of the corresponding source or drain regions, in addition to top surfaces of those source or drain regions. For example, during formation of the above discussed monolithic and continuous source or drain contact structure (e.g., through which the gate cut structure later extends), a space laterally between the first source or drain region and the second source or drain region is at least in part filled with the continuous source or drain contact structure. So, the continuous source or drain contact structure is on upper surfaces of the first and second source or drain regions, and also on sidewalls of the first and second source or drain regions. For instance, in one such example, the first source or drain region has (i) a first sidewall facing the second source or drain region, and (ii) an opposing second sidewall. Similarly, the second source or drain region has (i) a third sidewall facing the first source or drain region, and (ii) an opposing fourth sidewall. In an example, a portion of the continuous source or drain contact structure is on the first sidewall of the first source or drain region, and is also on the third sidewall of the second source or drain region. Accordingly, even after the continuous source or drain contact structure is bifurcated by the gate cut, a portion of the first source or drain contact may remain on the first sidewall of the first source or drain, and similarly, a portion of the second source or drain contact may remain on the third sidewall of the second source or drain. Having a source or drain contact on a sidewall (in addition to an upper surface) of a corresponding source or drain region effectively increases contact surface area and may therefore help to decrease contact resistance, without a corresponding increase in capacitance, thereby resulting in performance gain.
In an example, the above discussed at least in part wrapping of the source or drain contact on a sidewall of the corresponding source or drain region is independent of formation of the above discussed bridge contact. Thus, irrespective of whether the bridge contact is formed or not, a source or drain contact adjacent to a gate cut may be on a sidewall (as well as an upper surface) of the corresponding source or drain region. Thus, while the bridge contact between the first and second source or drain regions may be formed in one embodiment, the bridge contact may be absent between the first and second source or drain regions in another embodiment—however, for both cases, each of the first and second source or drain regions may be on a corresponding sidewall of a corresponding source or drain region. Moreover, note that the process margin for a process to deposit a larger diffusion contact across first and second diffusion regions and that is later divided into two diffusion contacts by a gate cut may be more forgiving than the process margin associated with a process designed to land a smaller diffusion contact on a single diffusion region. Similarly, device performance variation may also be reduced by the process to deposit a larger diffusion contact across first and second diffusion regions and that is later divided into two diffusion contacts by the gate cut.
The use of “group IV semiconductor material” (or “group IV material” or generally, “IV”) herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), and so forth. The use of “group III-V semiconductor material” (or “group III-V material” or generally, “III-V”) herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), gallium nitride (GaN), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example.
Materials that are “compositionally different” or “compositionally distinct” as used herein refers to two materials that have different chemical compositions. This compositional difference may be, for instance, by virtue of an element that is in one material but not the other (e.g., SiGe is compositionally different than silicon), or by way of one material having all the same elements as a second material but at least one of those elements is intentionally provided at a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different than from SiGe having 25 atomic percent germanium). In addition to such chemical composition diversity, the materials may also have distinct dopants (e.g., gallium and magnesium) or the same dopants but at differing concentrations. In still other embodiments, compositionally distinct materials may further refer to two materials that have different crystallographic orientations. For instance, (110) silicon is compositionally distinct or different from (100) silicon. Creating a stack of different orientations could be accomplished, for instance, with blanket wafer layer transfer. If two materials are elementally different, then one of the material has an element that is not in the other material.
Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. For example, in some embodiments, such tools may be used to detect a first transistor device having a first source or drain region, a laterally adjacent second transistor device having a second source or drain region, a first source or drain contact of the first source or drain region, a second source or drain contact of the second source or drain region, a gate cut structure comprising dielectric material laterally between the first and second source or drain contacts. In some examples, a bridge contact extends from an upper surface of the first source or drain contact to an upper surface of the second source or drain contact, although the bridge contact may be absent in another example. In an example, the first source or drain region includes a first sidewall facing the second source or drain region, and an opposing second sidewall. The first source or drain contact is on the first sidewall of the first source or drain region (e.g., along with an upper surface of the first source or drain region). In an example, the first source or drain contact may be absent on the second sidewall of the first source or drain region. In another example, a portion of the first source or drain contact may be on the second sidewall, but a width of the first source or drain contact on the second sidewall may be less than a width of the first source or drain contact on the first sidewall by at least 2 nanometers (nm), or at least 4 nm, or at least 6 nm, or at least 8 nm, or at least 10 nm. Numerous configurations and variations will be apparent in light of this disclosure.
The cross-sectional view of
Note that the perspective view of
In the plan or top view of
In an example, each of semiconductor devices 101a, 101b may be non-planar metal oxide semiconductor (MOS) transistors, such as tri-gate (e.g., finFET) or gate-all-around (GAA) transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The illustrated embodiments herein use the GAA structure including nanoribbons 104a, 104b as channel regions. The term nanoribbon may also encompass other similar GAA channel region shapes such as nanowires or nanosheets. Note that the nanoribbons of a device may be replaced by a fin-based structured in one example, to form a finFET device.
The various illustrated semiconductor devices represent a portion of an integrated circuit that may contain any number of similar semiconductor devices. Thus, although two example devices 101a, 101b are illustrated, there may be additional devices.
Each of devices 101a, 101b includes corresponding one or more nanoribbons 104a, 104b, respectively, that extend parallel to one another along an X-axis direction, between source and drain regions 130 (e.g., a first direction into and out of the page in the cross-section view of
As can be seen, devices 101 are formed on a substrate 102. Any number of semiconductor devices 101 can be formed on substrate 102, but two are illustrated here as an example. Substrate 102 can be, for example, a bulk substrate including group IV semiconductor material (such as silicon, germanium, or silicon germanium), group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and/or any other suitable material upon which transistors can be formed. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, a lower portion of (or all of) substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing, during a backside process.
As can further be seen, adjacent semiconductor devices are separated by a dielectric fill 106. Dielectric fill 106 provides shallow trench isolation (STI) between any adjacent semiconductor devices. Dielectric fill 106 can be any suitable dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON), for example.
The structure 100 comprises sub-fin regions 108a, 108b, such that the devices 104a, 104b each include a corresponding sub-fin region 108. According to some embodiments, sub-fin regions 108 comprise the same semiconductor material as substrate 102 and is adjacent to dielectric fill 106. According to some embodiments, nanoribbons 104 (or other semiconductor bodies, such as nanowires, nanosheets, or fin-based structures) extend between source and drain regions (illustrated in
Referring to
According to some embodiments, source or drain regions 130a, 130b, 131a, 131b are epitaxial regions that are provided using an etch-and-replace process. In other embodiments source or drain regions 130, 131 could be, for example, implantation-doped native portions of the semiconductor fins or substrate. Any semiconductor materials suitable for source and drain regions can be used (e.g., group IV and group III-V semiconductor materials). Source or drain regions may include multiple layers such as liners and capping layers to improve contact resistance. In any such cases, the composition and doping of source or drain regions may be the same or different, depending on the polarity of the transistors. In an example, for instance, one of the devices 101a, 101b is a p-type MOS (PMOS) transistor, an adjacent one of the devices is an n-type MOS (NMOS) transistor, and so on. Any number of source and drain configurations and materials can be used.
According to some embodiments, individual gate structures 125a, 125b extend over corresponding nanoribbons 104 along a second direction (e.g., in the direction of the Y-axis and across the page of
In one embodiment, each gate structure 125a, 125b includes a gate dielectric 116 that wraps around middle portions of each nanoribbon 104, and a gate electrode 118 that wraps around the gate dielectric 116. For example, gate structure 125a includes gate dielectric 116a wrapping around nanoribbons 104a, and gate electrode 118a. Similarly, gate structure 125b includes gate dielectric 116b wrapping around nanoribbons 104b, and gate electrode 118b.
In some embodiments, the gate dielectric 116 may include a single material layer or multiple stacked material layers. The gate dielectric 116 may include, for example, any suitable oxide (such as silicon dioxide), high-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. The high-k dielectric material (e.g., hafnium oxide) may be doped with an element to affect the threshold voltage of the given semiconductor device. According to some embodiments, the doping element used in gate dielectric 116 is lanthanum. In some embodiments, the gate dielectric can be annealed to improve its quality when high-k dielectric material is used. In some embodiments, the gate dielectric 116 includes a first layer (e.g., native oxide of nanoribbons, such as silicon dioxide or germanium oxide or SiGe-oxide) on the nanoribbons, and a second layer of high-k dielectric (e.g., hafnium oxide) on the first layer. The gate dielectric 116 is present around middle portions of each nanoribbon. In an example, the gate dielectric 116 may also be present over sub-fin 108, and/or on inner sidewalls of inner gate spacers (not illustrated).
The gate electrode 118a of the gate structure 125a wraps around middle portions of individual nanoribbons 104a, and the gate electrode 118b of the gate structure 125b wraps around middle portions of individual nanoribbons 104b. Note that the middle portion of each nanoribbon 104 is between a corresponding first end portion and a second end portion, where the first end portions of the nanoribbons of a stack is wrapped around by a corresponding first inner gate spacer 134, and where the second end portions of the nanoribbons of the stack is wrapped around by a corresponding second inner gate spacer 134. Inner gate spacers 134 can include any suitable dielectric material, such as silicon oxide or silicon nitride
In one embodiment, one or more work function materials may be included around the nanoribbons 104. Note that work function materials are called out separately, but may be considered to be part of the gate electrodes. In this manner, a gate electrode 118 may include multiple layers or components, including one or more work function materials, gate fill material, capping or resistance-reducing material, to name a few examples. In some embodiments, a p-channel device may include a work function metal having titanium, and an n-channel device may include a work function metal having tungsten or aluminum, although other material and combination may also be possible. In some other embodiments, the work function metal may be absent around one or more nanoribbons. In still other embodiments, there may be insufficient room for any gate fill material, after deposition of work function material (i.e., a given gate electrode may be all work function material and no fill material). In an example, the gate electrodes 118 may include any sufficiently conductive material, such as a metal, metal alloy, or doped polysilicon. The gate electrodes may include a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, cobalt, molybdenum, titanium nitride, or tantalum nitride, for example. Numerous gate structure configurations can be used along with the techniques provided herein, and the present disclosure is not intended to be limited to any particular such configurations.
As further shown in this example, adjacent gate structures 125a, 125b are separated laterally by a gate cut 122, which acts like a dielectric barrier between gate structures 125a, 125b. The gate cut 122 comprise a corresponding structure of sufficiently insulating material, such as a structure of dielectric material 114. Example dielectric materials 114 for gate cut 122 include silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON), e.g., include silicon and one or more of oxygen, carbon, or nitrogen. In some cases, gate cuts 122 may include multiple layers of dielectric material, such as a first layer of high-k dielectric material along the outer sidewalls of the gate cut structure, and a second layer or body of low-k dielectric material that fills in the remaining portion of the gate cut 122. In some examples, the gate cut 122 may include one or more airgaps or voids (e.g., filled with gas such as oxygen and/or nitrogen, or devoid of gas). More generally, the gate cut 122 may include any number of dielectric layers or bodies, and the overall gate cut structure can vary from one embodiment to the next. In an example, since the gate cut 122 is formed after the formation of the gate structures, gate dielectric 116 are not present along the sidewalls of gate cut 122 within the gate trench.
According to some embodiments, the gate cut 122 also extends such that it may cut across a portion of source or drain contacts 138a, 138b, as illustrated in
Thus, the gate cut 122 separates the contact 138a contacting the source or drain region 130a from the contact 138b contacting the source or drain region 130b. However, the circuit design may necessitate that the source or drain regions 130a and 130b be coupled to each other. Accordingly, as the gate cut separates the contacts 138a, 138b of the source or drain regions 130a, 130b, respectively, a bridge contact 140 is formed, as illustrated in
In one embodiment, a dielectric material 145 surrounds the source or drain regions 130a, 130b, and the contacts 138a, 138b, as illustrated in
In an example, the conductive contacts 138a, 138b, 140, 142 comprise an appropriate conductive material, such as one or more metals and/or alloys. Examples include, but are not limited to, pure copper, ruthenium, molybdenum, tungsten, cobalt, titanium, aluminum, an alloy such as copper-tin (CuSn), copper indium (CuIn), copper-antimony (CuSb), copper-bismuth (CuBi), copper-rhenium (CuRe), and/or any other suitable conductive material. In some embodiments, the conductive contacts include one or more of the same metal materials as gate electrode, or a different conductive material. Although not illustrated, in one embodiment, suitable barrier, liner or encapsulation layer may at least in part be around the conductive fill material of the conductive contacts 138a, 138b, 140, 142, e.g., to prevent diffusion of the conductive fill material of a contact to adjacent dielectric material.
The cross-sectional view of
However, in the structure 100, a gate cut 122 extends through the gate structures of the devices 101a, 101b. In contrast, there is no gate cut extending though a gate structure of the devices 201a, 201b. Accordingly, a common gate structure 225 comprising a common and continuous gate electrode 218 is on (e.g., at least partially or fully wraps around) the nanoribbons 204a and 204b, as illustrated in
The structure 300 includes source or drain regions 130a, 130b, 330a, and 330b of adjacent devices 101a, 101b, 301a, and 301b, respectively. As discussed with respect to
The source or drain regions 130a, 130b are separated from each other by a distance L1, and similarly, the source or drain regions 330a, 330b are separated from each other by a distance L2, as illustrated in
In one embodiment, the distance L2 may not be sufficient for the contacts 338a and/or 338b to respectively be on side surfaces of the source or drain regions 330a, 330b. For example, in the orientation of
In contrast, the contact 138a is on side surfaces of the source or drain region 130a, and the contact 138b is on side surfaces of the source or drain region 130b. For example, the contacts 138a, 138b are anyway going to be conjoined or connected to form a single continuous contact 138, which is later severed or bifurcated by the gate cut 122 into two separate contacts 138a, 138b. Accordingly, the contact 138a may have a width of w1 on a side surface of the source or drain region 130a facing the source or drain region 130b (and similarly, the contact 138b may have a similar width on a side surface of the source or drain region 130b facing the source or drain region 130a).
Thus, a surface area of a bottom surface of a portion of each of the contacts 138a, 138b, which is on a sidewall of the corresponding source or drain regions, is substantially greater (e.g., at least 5%, or at least 10%, or at least 15%, or at least 20%, or at least 25%) than a bottom surface of a portion of the contacts 330a, 330b that is on the sidewalls of the corresponding source or drain regions. Note that in the example of
For example, a left side of the contact 138a, which is on the left side surface of the source or drain contact 130a, has a first width w1; and a right side of the contact 138a, which is on the right side surface of the source or drain contact 130a, has a second width w2. In an example, the width w1 is substantially greater (e.g., at least 5%, or at least 10%, or at least 15%, or at least 20%, or at least 25%, or at least 1 nm, or at least 2 nm, or at least 4 nm, or at least 5 nm, or at least 7 nm, or at least 10 nm, or at least 12 nm) than the width w2.
The plan views of FIGS. 3C1 and 3C2 are along line M-M′ of
Note that in an example, widths w2 and w3 can be zero, as illustrated in the example of FIG. 3C2. In the example of FIG. 3C1, widths w2 and w3 can be at most 1 nm, or at most 2 nm, or at most 3 nm. In contrast, the width w1 may be at least 1 nm, or at least 2 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm, or at least 6 nm, or at least 7 nm, or at least 10 nm, or at least 12 nm. In an example, the width w1 may be greater than one or both of w2 and w3 by at least 1 nm, or at least 2 nm, or at least 3 nm, or at least 4 nm, or at least 5 nm, or at least 6 nm, or at least 7 nm, or at least 10 nm, or at least 12 nm. Note that width w3 is zero in the example of
In the example of
In the structure 100 of
In an example, the circuit design dictates that the contacts 438a and 438b are separated. So, the contacts 438a and 438b could have been formed similar to the contacts 338a and 338b (e.g., not conjoined even prior to the gate cut process). However, for reasons discussed with respect to
For example, the contacts 538a, 538b are respectively above corresponding source or drain regions 530a, 530b, and are respectively similar to the corresponding contacts 138a, 138b of
Note that each of the contacts 538a, 538b, 538c, and 538d have a corresponding portion of a corresponding sidewall of the corresponding source or drain region, where the portion has a width of w1, as illustrated in
Referring to
The method 600 then proceeds from 604 to 608. At 608, recesses 710, 712, and 714 are formed within the dielectric material 745, as illustrated in
The method 600 then proceeds from 608 to 612. At 612, the recesses 710, 712, 714 are filled with conductive material, to respectively form the source or drain contacts 738, 748b, 748a. As illustrated in
The method 600 then proceeds from 612 to 616. At 616, a recess 720 is formed, where the recess 720 extends through a gate structure of the devices 701c, 701d, and also extends though the source or drain contact 738, thereby bifurcating the source or drain contact 738 into separate contacts 738a, 738b. For example,
The method 600 then proceeds from 616 to either of 620a or 620b. For example, process 620a results in the structures illustrated in
Referring now to 620a of the method 600, a bridge contact 740 is formed, where the bridge contact 740 couples the contacts 738a, 738b, as illustrated in
Referring now to 620b (which may be performed as an alternative to 620a) of the method 600, conductive contacts 752a, 752b, 742b are formed, which are respectively coupled to the contacts 738a, 738b, 748b, as illustrated in
Thus, while the structure of
Note that the processes in method 600 are shown in a particular order for ease of description. However, one or more of the processes may be performed in a different order or may not be performed at all (and thus be optional), in accordance with some embodiments. Numerous variations on method 600 and the techniques described herein will be apparent in light of this disclosure.
Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term “processor” may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi-standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.
In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.
The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.
Example 1. An integrated circuit comprising: a first device including (i) a first source or drain region, (ii) a first body of semiconductor material extending laterally from the first source or drain region, (iii) a first gate structure on the first body, and (iv) a first contact extending vertically upward from the first source or drain region; a second device including (i) a second source or drain region, (ii) a second body of semiconductor material extending laterally from the second source or drain region, (iii) a second gate structure on the second body, and (iv) a second contact extending vertically upward from the second source or drain region; a gate cut structure comprising dielectric material laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact; and a third contact extending laterally from the first contact to the second contact and over the gate cut structure.
Example 2. The integrated circuit of claim 1, wherein the third contact extends laterally from an upper surface of the first contact to an upper surface of the second contact.
Example 3. The integrated circuit of any one of claims 1-2, further comprising: a third device including (i) a third source or drain region, and (ii) a third body of semiconductor material extending laterally from the third source or drain region, wherein the first gate structure is on the third body, and wherein the first contact extends vertically upward from the third source or drain region.
Example 4. The integrated circuit of any one of claims 1-2, further comprising: a third device including (i) a third source or drain region, (ii) a third body of semiconductor material extending laterally from the third source or drain region, (iii) a third gate structure on the third body, and (iv) a fourth contact extending vertically upward from the third source or drain region; wherein a portion of the first contact, which is on a sidewall of the first source or drain region, has a first width; and wherein a portion of the fourth contact, which is on a sidewall of the third source or drain region, has a second width that is at least 2 nanometers less than the first width.
Example 5. The integrated circuit of any one of claims 1-4, wherein: the first source or drain region has a first sidewall facing the second source or drain region, and a second sidewall that is on an opposite side of the first sidewall; a first portion of the first contact, which is on the first sidewall of the first source or drain region, has a first width; and a second portion of the first contact, which is on the second sidewall of the first source or drain region, has a second width that is at least 2 nanometers less than the first width.
Example 6. The integrated circuit of any one of claims 1-5, wherein the second width is at least 5 nanometers less than the first width.
Example 7. The integrated circuit of any one of claims 1-6, wherein: the first source or drain region has a first sidewall facing the second source or drain region, and a second sidewall that is on an opposite side of the first sidewall; a portion of the first contact is on the first sidewall of the first source or drain region; and no portion of the first contact is on the second sidewall of the first source or drain region.
Example 8. The integrated circuit of any one of claims 1-7, wherein each of the first body and the second body is a nanoribbon, a nanosheet, or a nanowire.
Example 9. The integrated circuit of any one of claims 1-8, wherein each of the first body and the second body is a fin.
Example 10. The integrated circuit of any one of claims 1-9, wherein the gate cut structure is also laterally between the first source or drain region and the second source or drain region.
Example 11. The integrated circuit of any one of claims 1-10, wherein the gate cut structure is a continuous structure of the dielectric material that is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact
Example 12. The integrated circuit of any one of claims 1-11, wherein the first contact comprises: conductive fill material; and a conductive liner layer of one or more walls of the first contact.
Example 13. The integrated circuit of claim 12, wherein the conductive liner layer is present between the conductive fill material of the first contact and at least a section of the first source or drain region, and the conductive liner layer is absent between the conductive fill material of the first contact and at least a section of the gate cut structure.
Example 14. A printed circuit board comprising the integrated circuit of any one of claims 1-13.
Example 15. An integrated circuit comprising: a first device including (i) a first source or drain region, (ii) a first gate structure, and (iii) a first contact extending above from the first source or drain region; a second device including (i) a second source or drain region, (ii) a second gate structure, and (ii) a second contact extending above from the second source or drain region; a third device including (i) a third source or drain region, (ii) a third gate structure, and (ii) a third contact extending above from the third source or drain region; and gate cut comprising dielectric material laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact; wherein a portion of the first contact that is on a sidewall of the first source or drain region has a first width; wherein a portion of the third contact that is on a sidewall of the third source or drain region has a second width; and the first width is greater than the second width by at least 2 nanometers.
Example 16. The integrated circuit of claim 15, wherein the second width is less than 1 nm.
Example 17. The integrated circuit of any one of claims 15-16, wherein the first width is greater than the second width by at least 4 nanometers.
Example 18. The integrated circuit of any one of claims 15-17, wherein: the portion of the first contact having the first width is a first portion; the sidewall of the first source or drain region, on which the first portion of the first contact having the first width is located, is a first sidewall of the first source or drain region; the first sidewall of the first source or drain region faces the gate cut and the second source or drain region; the first source or drain region has a second sidewall opposite the first sidewall; a second portion of the first contact that is on the second sidewall of the first source or drain region has a third width; and the first width is greater than the third width by at least 2 nanometers.
Example 19. The integrated circuit of any one of claims 15-18, wherein: the sidewall of the first source or drain region, on which the portion of the first contact having the first width is located, is a first sidewall of the first source or drain region; the first sidewall of the first source or drain region faces the gate cut and the second source or drain region; the first source or drain region has a second sidewall opposite the first sidewall; and no portion of the first contact is on the second sidewall of the first source or drain region.
Example 20. The integrated circuit of any one of claims 15-19, further comprising: a fourth contact extending laterally from an upper surface of the first contact to an upper surface of the second contact, wherein the fourth contact is above a portion of the gate cut.
Example 21. An integrated circuit comprising: a first source or drain region, and a first contact that is in contact with top and side surfaces of the first source or drain region; a second source or drain region, and a second contact that is in contact with top and side surfaces of the second source or drain region; and a gate cut structure extending laterally between the first contact and the second contact; and wherein each of the side surface of the first source or drain region and the side surface of the second source or drain region are facing the gate cut structure.
Example 22. The integrated circuit of claim 21, further comprising: a conductive structure extending laterally from an upper surface of the first contact to an upper surface of the second contact, the conductive structure extending above the gate cut structure.
Example 23. The integrated circuit of any one of claims 21-22, further comprising: a first body of semiconductor material extending laterally from the first source or drain region, and a first gate structure on the first body; a second body of semiconductor material extending laterally from the second source or drain region, and a second gate structure on the second body; wherein the gate cut structure extends laterally between the first gate structure and the second gate structure.
Example 24. The integrated circuit of any one of claims 21-23, wherein: the first source or drain region has a first sidewall facing the second source or drain contact, and an opposing second sidewall; a first portion of the first contact, that is on the first sidewall of the first source or drain region, has a first width; a second portion of the first contact, that is on the second sidewall of the first source or drain region, has a second width; and the first width is greater than the second width by at least 2 nanometers.
The foregoing description of example embodiments of the present disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto.
