Atul Ajmera

Person

Wappinger, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Spacer and process to enhance the strain in the channel with stress...
- Patent number 8,461,009
- Issue date Jun 11, 2013
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor devices using embedded L-shape spa...
- Patent number 7,759,206
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polycrystalline SiGe Junctions for advanced devices
- Patent number 7,741,165
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polycrystalline SiGe junctions for advanced devices
- Patent number 7,387,924
- Issue date Jun 17, 2008
- International Business Machines Corporation
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polycrystalline SiGe junctions for advanced devices
- Patent number 7,135,391
- Issue date Nov 14, 2006
- International Business Machines Corporation
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for avoiding oxide undercut during pre-silicide clean for th...
- Patent number 7,091,128
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for avoiding oxide undercut during pre-silicide clean for th...
- Patent number 6,991,979
- Issue date Jan 31, 2006
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface engineering to prevent epi growth on gate poly during selec...
- Patent number 6,900,092
- Issue date May 31, 2005
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming heavy nitrogen-doped ultra thin oxynitride gate...
- Patent number 6,642,156
- Issue date Nov 4, 2003
- International Business Machines Corporation
- Evgeni Gousev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an oxide film on a gate side wall of a gate struc...
- Patent number 6,605,521
- Issue date Aug 12, 2003
- Kabushiki Kaisha Toshiba
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation for thin silicon/silicon-on-insulator subs...
- Patent number 6,602,759
- Issue date Aug 5, 2003
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of improving gate activation by employing atomic oxygen enha...
- Patent number 6,566,210
- Issue date May 20, 2003
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure with non-epitaxial raised source/drain and self-alig...
- Patent number 6,566,198
- Issue date May 20, 2003
- International Business Machines Corporation
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of integrating substrate contact on SOI wafers with STI process
- Patent number 6,521,947
- Issue date Feb 18, 2003
- International Business Machines Corporation
- Atul Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming notch gate having self-aligned raised source/dra...
- Patent number 6,506,649
- Issue date Jan 14, 2003
- International Business Machines Corporation
- Ka Hing Fung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned silicide (salicide) process for strained silicon MOSFE...
- Patent number 6,503,833
- Issue date Jan 7, 2003
- International Business Machines Corporation
- Atul Champaklal Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface engineering to prevent EPI growth on gate poly during selec...
- Patent number 6,440,807
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant sidewall spacer using notch gate process
- Patent number 6,437,377
- Issue date Aug 20, 2002
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing patterned silicon-on-insulator layers wit...
- Patent number 6,255,145
- Issue date Jul 3, 2001
- International Business Machines Corporation
- Atul Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Titanium polycide stabilization with a porous barrier
- Patent number 6,057,220
- Issue date May 2, 2000
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature BPSG deposition process
- Patent number 6,013,583
- Issue date Jan 11, 2000
- International Business Machines Corporation
- Atul C. Ajmera
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow...
- Patent number 5,747,866
- Issue date May 5, 1998
- Siemens Aktiengesellschaft
- Herbert Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow...
- Patent number 5,643,823
- Issue date Jul 1, 1997
- Siemens Aktiengesellschaft
- Herbert Ho
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS...
- Publication number 20130256766
- Publication date Oct 3, 2013
- International Business Machines Corporation
- Atul C. AJMERA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polycrystalline SiGe Junctions for Advanced Devices
- Publication number 20080248635
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN IMPLANTATION AND CHANNEL STRAIN TRANSFER USING DIFFERE...
- Publication number 20070254420
- Publication date Nov 1, 2007
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS...
- Publication number 20070202654
- Publication date Aug 30, 2007
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR DEVICES USING EMBEDDED L-SHAPE SPA...
- Publication number 20070122988
- Publication date May 31, 2007
- International Business Machines Corporation
- Zhijiong Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polycrystalline SiGe junctions for advanced devices
- Publication number 20070010076
- Publication date Jan 11, 2007
- International Business Machines Corporation
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for avoiding oxide undercut during pre-silicide clean for th...
- Publication number 20060057797
- Publication date Mar 16, 2006
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polycrystalline SiGe junctions for advanced devices
- Publication number 20050260832
- Publication date Nov 24, 2005
- Kevin Kok Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR TH...
- Publication number 20050064635
- Publication date Mar 24, 2005
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned silicide (salicide) process for strained silicon MOSFE...
- Publication number 20030068883
- Publication date Apr 10, 2003
- International Business Machines Corporation
- Atul Champaklal Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an oxide film on a gate side wall of a gate struc...
- Publication number 20030036253
- Publication date Feb 20, 2003
- KABUSHIKI KAISHA TOSHIBA
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming heavy nitrogen-doped ultra thin oxynitride gate...
- Publication number 20030027392
- Publication date Feb 6, 2003
- International Business Machines Corporation
- Evgeni Gousev
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF IMPROVING GATE ACTIVATION BY EMPLOYING ATOMIC OXYGEN ENHA...
- Publication number 20030010972
- Publication date Jan 16, 2003
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Surface engineering to prevent epi growth on gate poly during selec...
- Publication number 20020192888
- Publication date Dec 19, 2002
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS structure with non-epitaxial raised source/drain and self-alig...
- Publication number 20020142551
- Publication date Oct 3, 2002
- International Business Machines Corporation
- Heemyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRA...
- Publication number 20020132431
- Publication date Sep 19, 2002
- International Business Machines Corporation
- Ka Hing Fung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW DIELECTRIC CONSTANT SIDEWALL SPACER USING NOTCH GATE PROCESS
- Publication number 20020096695
- Publication date Jul 25, 2002
- International Business Machines Corporation
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shallow trench isolation for thin silicon/silicon-on-insulator subs...
- Publication number 20020072196
- Publication date Jun 13, 2002
- Atul C. Ajmera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planar substrate with patterned silicon-on- insulator region and se...
- Publication number 20010041395
- Publication date Nov 15, 2001
- Atul Ajmera
- H01 - BASIC ELECTRIC ELEMENTS

Atul Ajmera

Person

Patents Grantslast 30 patents

Spacer and process to enhance the strain in the channel with stress...

Methods of forming semiconductor devices using embedded L-shape spa...

Polycrystalline SiGe Junctions for advanced devices

Polycrystalline SiGe junctions for advanced devices

Polycrystalline SiGe junctions for advanced devices

Method for avoiding oxide undercut during pre-silicide clean for th...

Method for avoiding oxide undercut during pre-silicide clean for th...

Surface engineering to prevent epi growth on gate poly during selec...

Method for forming heavy nitrogen-doped ultra thin oxynitride gate...

Method of forming an oxide film on a gate side wall of a gate struc...

Shallow trench isolation for thin silicon/silicon-on-insulator subs...

Method of improving gate activation by employing atomic oxygen enha...

CMOS structure with non-epitaxial raised source/drain and self-alig...

Method of integrating substrate contact on SOI wafers with STI process

Method for forming notch gate having self-aligned raised source/dra...

Self-aligned silicide (salicide) process for strained silicon MOSFE...

Surface engineering to prevent EPI growth on gate poly during selec...

Low dielectric constant sidewall spacer using notch gate process

Process for manufacturing patterned silicon-on-insulator layers wit...

Titanium polycide stabilization with a porous barrier

Low temperature BPSG deposition process

Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow...

Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow...

Patents Applicationslast 30 patents

SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS...

Polycrystalline SiGe Junctions for Advanced Devices

SOURCE/DRAIN IMPLANTATION AND CHANNEL STRAIN TRANSFER USING DIFFERE...

SPACER AND PROCESS TO ENHANCE THE STRAIN IN THE CHANNEL WITH STRESS...

METHODS OF FORMING SEMICONDUCTOR DEVICES USING EMBEDDED L-SHAPE SPA...

Polycrystalline SiGe junctions for advanced devices

Method for avoiding oxide undercut during pre-silicide clean for th...

Polycrystalline SiGe junctions for advanced devices

METHOD FOR AVOIDING OXIDE UNDERCUT DURING PRE-SILICIDE CLEAN FOR TH...

Self-aligned silicide (salicide) process for strained silicon MOSFE...

Method of forming an oxide film on a gate side wall of a gate struc...

Method for forming heavy nitrogen-doped ultra thin oxynitride gate...

METHOD OF IMPROVING GATE ACTIVATION BY EMPLOYING ATOMIC OXYGEN ENHA...

Surface engineering to prevent epi growth on gate poly during selec...

CMOS structure with non-epitaxial raised source/drain and self-alig...

METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRA...

LOW DIELECTRIC CONSTANT SIDEWALL SPACER USING NOTCH GATE PROCESS

Shallow trench isolation for thin silicon/silicon-on-insulator subs...

Planar substrate with patterned silicon-on- insulator region and se...