Barry Britton

Person

Orefield, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single event upset immune flip-flop utilizing a small-area highly r...
- Patent number 10,819,318
- Issue date Oct 27, 2020
- Microchip Technology Inc.
- Barry Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop circuit with selectable feedback paths
- Patent number 8,531,222
- Issue date Sep 10, 2013
- Lattice Semiconductor Corporation
- Barry Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Safe programming of key information into non-volatile memory for a...
- Patent number 8,319,521
- Issue date Nov 27, 2012
- Lattice Semiconductor Corporation
- Wei Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power control block with output glitch protection
- Patent number 8,314,634
- Issue date Nov 20, 2012
- Lattice Semiconductor Corporation
- Barry Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible delay cell architecture
- Patent number 7,863,931
- Issue date Jan 4, 2011
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with multiple slice types
- Patent number 7,696,784
- Issue date Apr 13, 2010
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-slice architectures for programmable logic devices
- Patent number 7,675,321
- Issue date Mar 9, 2010
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable interconnect for reconfigurable system-on-chip
- Patent number 7,650,545
- Issue date Jan 19, 2010
- Agere Systems Inc.
- Miron Abramovici
- G01 - MEASURING TESTING
Information Patent Grant
Area efficient routing architectures for programmable logic devices
- Patent number 7,605,606
- Issue date Oct 20, 2009
- Lattice Semiconductor Corporation
- Ming H. Ding
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock-and-data-recovery system having a multi-phase clock generator...
- Patent number 7,599,457
- Issue date Oct 6, 2009
- Lattice Semiconductor Corporation
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Logic block control architectures for programmable logic devices
- Patent number 7,592,834
- Issue date Sep 22, 2009
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient configuration of daisy-chained programmable logic devices
- Patent number 7,554,357
- Issue date Jun 30, 2009
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed multiple-channel alignment scheme
- Patent number 7,532,646
- Issue date May 12, 2009
- Lattice Semiconductor Corporation
- Wai-Bor Leung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Logic block control architectures for programmable logic devices
- Patent number 7,397,276
- Issue date Jul 8, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual slice architectures for programmable logic devices
- Patent number 7,385,417
- Issue date Jun 10, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architecture with multiple slice types
- Patent number 7,378,872
- Issue date May 27, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable termination for single-ended and differential schemes
- Patent number 7,262,630
- Issue date Aug 28, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protocol-independent packet delineation for backplane architecture
- Patent number 7,139,288
- Issue date Nov 21, 2006
- Agere Systems Inc.
- Francois Balay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive input logic for phase adjustments
- Patent number 7,034,596
- Issue date Apr 25, 2006
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable broadcast initialization of memory blocks
- Patent number 6,940,779
- Issue date Sep 6, 2005
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for controlling signal distribution in an elec...
- Patent number 6,873,187
- Issue date Mar 29, 2005
- Lattice Semiconductor Corporation
- William Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-master multi-slave system bus in a field programmable gate ar...
- Patent number 6,483,342
- Issue date Nov 19, 2002
- Lattice Semiconductor Corporation
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate input and output in a programmable logic device
- Patent number 6,472,904
- Issue date Oct 29, 2002
- Lattice Semiconductor Corporation
- William B. Andrews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array having a dedicated processor interface
- Patent number 6,216,191
- Issue date Apr 10, 2001
- Lucent Technologies Inc.
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global signal distribution with reduced routing tracks in an FPGA
- Patent number 6,064,225
- Issue date May 16, 2000
- Lucent Technologies Inc.
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable clock manager for a programmable logic device that can...
- Patent number 6,060,902
- Issue date May 9, 2000
- Lucian R. Albu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with logic cells having a flexible input...
- Patent number 6,049,224
- Issue date Apr 11, 2000
- Lucent Technologies Inc.
- Barry K. Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable clock manager for a programmable logic device that can...
- Patent number 6,043,677
- Issue date Mar 28, 2000
- Lucent Technologies Inc.
- Lucian R. Albu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable clock manager for a programmable logic device that can...
- Patent number 6,028,463
- Issue date Feb 22, 2000
- Lucent Technologies Inc.
- Lucian R. Albu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid programmable gate arrays
- Patent number 6,020,755
- Issue date Feb 1, 2000
- Lucent Technologies Inc.
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS
- Publication number 20140009194
- Publication date Jan 9, 2014
- Lattice Semiconductor Corporation
- Barry Britton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Efficient configuration of daisy-chained programmable logic devices
- Publication number 20070182445
- Publication date Aug 9, 2007
- Zheng (Jeff) Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock-and-data-recovery system having a multi-phase clock generator...
- Publication number 20070030936
- Publication date Feb 8, 2007
- Phillip Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Distributed multiple-channel alignment scheme
- Publication number 20060187966
- Publication date Aug 24, 2006
- Wai-Bor Leung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable broadcast initialization of memory blocks
- Publication number 20050035781
- Publication date Feb 17, 2005
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive input logic for phase adjustments
- Publication number 20040155690
- Publication date Aug 12, 2004
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Protocol-independent packet delineation for backplane architecture
- Publication number 20040071224
- Publication date Apr 15, 2004
- Francois Balay
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-master multi-slave system bus in a field programmable gate ar...
- Publication number 20020008540
- Publication date Jan 24, 2002
- Barry K. Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double data rate input and output in a programmable logic device
- Publication number 20020003436
- Publication date Jan 10, 2002
- William B. Andrews
- G06 - COMPUTING CALCULATING COUNTING

Barry Britton

Person

Patents Grantslast 30 patents

Single event upset immune flip-flop utilizing a small-area highly r...

Phase locked loop circuit with selectable feedback paths

Safe programming of key information into non-volatile memory for a...

Power control block with output glitch protection

Flexible delay cell architecture

Programmable logic device with multiple slice types

Dual-slice architectures for programmable logic devices

Programmable interconnect for reconfigurable system-on-chip

Area efficient routing architectures for programmable logic devices

Clock-and-data-recovery system having a multi-phase clock generator...

Logic block control architectures for programmable logic devices

Efficient configuration of daisy-chained programmable logic devices

Distributed multiple-channel alignment scheme

Logic block control architectures for programmable logic devices

Dual slice architectures for programmable logic devices

Programmable logic device architecture with multiple slice types

Programmable termination for single-ended and differential schemes

Protocol-independent packet delineation for backplane architecture

Adaptive input logic for phase adjustments

Programmable broadcast initialization of memory blocks

Method and apparatus for controlling signal distribution in an elec...

Multi-master multi-slave system bus in a field programmable gate ar...

Double data rate input and output in a programmable logic device

Field programmable gate array having a dedicated processor interface

Global signal distribution with reduced routing tracks in an FPGA

Programmable clock manager for a programmable logic device that can...

Programmable logic device with logic cells having a flexible input...

Programmable clock manager for a programmable logic device that can...

Programmable clock manager for a programmable logic device that can...

Hybrid programmable gate arrays

Patents Applicationslast 30 patents

PHASE LOCKED LOOP CIRCUIT WITH SELECTABLE FEEDBACK PATHS

Efficient configuration of daisy-chained programmable logic devices

Clock-and-data-recovery system having a multi-phase clock generator...

Distributed multiple-channel alignment scheme

Programmable broadcast initialization of memory blocks

Adaptive input logic for phase adjustments

Protocol-independent packet delineation for backplane architecture

Multi-master multi-slave system bus in a field programmable gate ar...

Double data rate input and output in a programmable logic device