Been-jon K. Woo

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned contact formation utilizing sacrificial polysilicon
- Patent number 7,632,736
- Issue date Dec 15, 2009
- Intel Corporation
- Max Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell having reduced floating gate to floating gate cou...
- Patent number 7,465,625
- Issue date Dec 16, 2008
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell having reduced floating gate to floating gate cou...
- Patent number 7,348,618
- Issue date Mar 25, 2008
- Intel Corporation
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicidation method for contactless EPROM related devices
- Patent number 5,470,772
- Issue date Nov 28, 1995
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Erase performance improvement via dual floating gate processing
- Patent number 5,229,631
- Issue date Jul 20, 1993
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a flash EPROM having reduced cell size
- Patent number 5,210,047
- Issue date May 11, 1993
- Been-Jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making source junction breakdown for devices with source-...
- Patent number 5,196,361
- Issue date Mar 23, 1993
- Intel Corporation
- Tong-Chern Ong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Erase performance improvement via dual floating gate processing
- Patent number 5,147,813
- Issue date Sep 15, 1992
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving device scalability of buried bit line flash EP...
- Patent number 5,102,814
- Issue date Apr 7, 1992
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving erase characteristics of buried bit line flash...
- Patent number 5,077,230
- Issue date Dec 31, 1991
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving erase characteristics of buried bit line flash...
- Patent number 5,075,245
- Issue date Dec 24, 1991
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten-silicide reoxidation process including annealing in pure n...
- Patent number 4,833,099
- Issue date May 23, 1989
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source drain doping technique
- Patent number 4,784,965
- Issue date Nov 15, 1988
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten-silicide reoxidation technique using a CVD oxide cap
- Patent number 4,774,201
- Issue date Sep 27, 1988
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source drain doping technique
- Patent number 4,757,026
- Issue date Jul 12, 1988
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a MOSFET with graded source and drain regions
- Patent number 4,728,617
- Issue date Mar 1, 1988
- Intel Corporation
- Been-Jon Woo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Self-aligned contact formation utilizing sacrificial polysilicon
- Publication number 20090155995
- Publication date Jun 18, 2009
- Max Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with buried source rail
- Publication number 20090001440
- Publication date Jan 1, 2009
- Max Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash memory cell having reduced floating gate to floating gate cou...
- Publication number 20070037350
- Publication date Feb 15, 2007
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash memory cell having reduced floating gate to floating gate cou...
- Publication number 20060228858
- Publication date Oct 12, 2006
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS

Been-jon K. Woo

Person

Patents Grantslast 30 patents

Self-aligned contact formation utilizing sacrificial polysilicon

Flash memory cell having reduced floating gate to floating gate cou...

Flash memory cell having reduced floating gate to floating gate cou...

Silicidation method for contactless EPROM related devices

Erase performance improvement via dual floating gate processing

Process for fabricating a flash EPROM having reduced cell size

Method of making source junction breakdown for devices with source-...

Erase performance improvement via dual floating gate processing

Method for improving device scalability of buried bit line flash EP...

Method for improving erase characteristics of buried bit line flash...

Method for improving erase characteristics of buried bit line flash...

Tungsten-silicide reoxidation process including annealing in pure n...

Source drain doping technique

Tungsten-silicide reoxidation technique using a CVD oxide cap

Source drain doping technique

Method of fabricating a MOSFET with graded source and drain regions

Patents Applicationslast 30 patents

Self-aligned contact formation utilizing sacrificial polysilicon

Semiconductor device with buried source rail

Flash memory cell having reduced floating gate to floating gate cou...

Flash memory cell having reduced floating gate to floating gate cou...