Claims
- 1. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) integrated circuit where at least two insulated gate members are formed on a portion of a semiconductor substrate, comprising the steps of:
- (a) forming a thermal oxidation insulating layer over said substrate, including over opposite sides and upper surfaces of a first and second gate members, said first gate member being formed on a first portion of said substrate and said second gate member being formed on a second portion of said substrate;
- (b) forming low-temperature oxide spacer members on said opposite sides of said first and second gate members over said insulating layer;
- (c) masking said second gate and said second portion of said substrate;
- (d) causing first ions of a conductivity type determining impurity of a first conductivity type to impinge on the structure resulting from step (c) surrounding said first gate, wherein ion implanted regions of said first ions are formed in said substrate surrounding said first gate, said spacers and first gate member functioning as a mask and preventing said first ions from reaching said substrate, such that first ion implanted regions are formed away from said substrate underlying said spacers and first gate member;
- (e) removing said spacers from about said first gate;
- (f) causing second ions of a conductivity type determining impurity of said first conductivity type to impinge on the structure resulting from step (e) surrounding only said first gate member wherein said first gate member functions to mask its underlying substrate from said second ions, such that second ion implanted regions are formed immediately adjacent to substrate underlying said first gate and having lower concentration of ions than substrate disposed further from said first gate member;
- (g) masking said first gate and said first portion of said substrate; and exposing said second gate and said second portion of said substrate;
- (h) etching selectively said thermal oxidation insulating layer and said spacers over said second portion of said substrate, such that all spacers are removed and portions of said thermal oxidation insulating layer previously underlying said spacers are at a larger thickness than said thermal oxidation insulating layer previously not underlying said spacers about said second gate;
- (i) causing third ions of a conductivity type determining impurity of a second conductivity type to impinge on the structure resulting from step (h) surrounding said second gate member, such that said substrate immediately adjacent to substrate underlying said second gate member and having lower concentration of ions than substrate disposed further from said second gate member;
- (j) heating said substrate to diffuse at least a portion of said ions of first conductivity type determining impurities underneath at least a portion of said first gate member and ions of said second conductivity type determining impurities underneath at least a portion of said second gate;
- whereby a CMOS integrated circuit is formed.
- 2. A method of fabricating a complimentary metal-oxide-semiconductor (CMOS) integrated circuit comprising the steps of:
- (a) forming a first insulated gate on a first region of a semiconductor substrate;
- (b) forming a second insulated gate on a second region of said substrate;
- (c) forming a thermal oxidation layer over said substrate and over the top and side wall surfaces of said first and second gates;
- (d) forming a low temperature oxidation layer over said thermal oxidation layer;
- (e) etching selectively a portion of said low temperature oxidation layer, wherein said low temperature oxidation layer remains on said side wall surfaces of said first and second gates to form spacers;
- (f) masking said second region;
- (g) causing first ions of a conductivity type determining impurity of a first conductivity type to impinge on the structure resulting from step (f), such that first ion implanted regions are formed in said first region away from said substrate underlying said spacers and said first gate;
- (h) removing said low temperature oxidation spacers from the side walls from said first gate;
- (i) causing second ions of a conductivity type determining impurity of said first conductivity type to impinge on the structure resulting from step (h) such that said substrate of said first region immediately adjacent to substrate underlying said first gate having a lower concentration of ions than substrate disposed further from said first gate;
- (j) masking said first regions and exposing said second region;
- (k) etching said low temperature oxidation layer and said thermal oxidation layer over said second region, such that all spacers are removed and portions of said thermal oxidation layer previously underlying said spacers are at a larger thickness than said thermal oxidation layer previously not underlying said spacers;
- (l) causing third ions of a conductivity type determining impurity of a second conductivity type to impinge on the structure resulting from step (k) such that said substrate immediately adjacent to substrate underlying said second gate having lower concentration of ions than substrate disposed further from said second gate;
- (m) heating to activate said ions of first and second conductivity type determining impurities by diffusing at least a portion of said ions of first conductivity type determining impurities underneath at least a portion of said first gate and diffusing said ions of second conductivity type determining impurities underneath at least a portion of said second gate;
- whereby a CMOS integrated circuit is formed.
Parent Case Info
This is a divisional of application Ser. No. 926,733 filed Nov. 4, 1986.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4366613 |
Ogura et al. |
Jan 1983 |
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4536944 |
Bracco et al. |
Aug 1985 |
|
4642878 |
Maeda |
Feb 1987 |
|
Non-Patent Literature Citations (1)
Entry |
Ghandhi, VLS1 Fabrication Principles, John Wiley and Sons, 1983, p. 230. |
Divisions (1)
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Number |
Date |
Country |
Parent |
926733 |
Nov 1986 |
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