Bogdan I. Georgescu

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
High voltage architecture for non-volatile memory
- Patent number 10,373,688
- Issue date Aug 6, 2019
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 10,262,747
- Issue date Apr 16, 2019
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 10,204,691
- Issue date Feb 12, 2019
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 10,032,517
- Issue date Jul 24, 2018
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 9,899,089
- Issue date Feb 20, 2018
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 9,847,137
- Issue date Dec 19, 2017
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage architecture for non-volatile memory
- Patent number 9,704,585
- Issue date Jul 11, 2017
- Cypress Semiconductor Corporation
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative high voltage hot switching circuit
- Patent number 9,608,615
- Issue date Mar 28, 2017
- Cypress Semiconductor Corporation
- Gary Peter Moscaluk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed, high voltage tolerant circuits in flash path
- Patent number 9,595,332
- Issue date Mar 14, 2017
- Cypress Semiconductor Corporation
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 9,431,124
- Issue date Aug 30, 2016
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for providing high voltage to memory devices
- Patent number 9,129,686
- Issue date Sep 8, 2015
- Cypress Semiconductor Corporation
- Ryan T Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 8,988,938
- Issue date Mar 24, 2015
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory devices and systems
- Patent number 8,908,438
- Issue date Dec 9, 2014
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for providing high voltage to memory devices
- Patent number 8,750,051
- Issue date Jun 10, 2014
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 8,675,405
- Issue date Mar 18, 2014
- Cypress Semiconductor Corp.
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage tolerant row driver
- Patent number 8,599,618
- Issue date Dec 3, 2013
- Cypress Semiconductor Corp.
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory devices and systems
- Patent number 8,570,809
- Issue date Oct 29, 2013
- Cypress Semiconductor Corp.
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 8,542,541
- Issue date Sep 24, 2013
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 8,125,835
- Issue date Feb 28, 2012
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having a reference current generator that provi...
- Patent number 7,969,804
- Issue date Jun 28, 2011
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power Bandgap reference circuit with increased accuracy and red...
- Patent number 7,683,701
- Issue date Mar 23, 2010
- Cypress Semiconductor Corporation
- Bogdan I. Georgescu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and circuit for high speed transmission gate logic
- Patent number 7,053,662
- Issue date May 30, 2006
- Cypress Semiconductor Corporation
- John Silver
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture, method(s) and circuitry for low power memories
- Patent number 6,674,682
- Issue date Jan 6, 2004
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE
Information Patent Grant
Block redundancy in ultra low power memory circuits
- Patent number 6,535,437
- Issue date Mar 18, 2003
- Cypress Semiconductor Corp.
- John J. Silver
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, method (s) and circuitry for low power memories
- Patent number 6,493,283
- Issue date Dec 10, 2002
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE
Information Patent Grant
Block redundancy in ultra low power memory circuits
- Patent number 6,249,464
- Issue date Jun 19, 2001
- Cypress Semiconductor Corp.
- John J. Silver
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, method(s) and circuitry for low power memories
- Patent number 6,163,495
- Issue date Dec 19, 2000
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR TESTING A NON-VOLATILE MEMORY
- Publication number 20240212781
- Publication date Jun 27, 2024
- Infineon Technologies LLC
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY
- Publication number 20200066352
- Publication date Feb 27, 2020
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Bogdan I. Georgescu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20180166140
- Publication date Jun 14, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20180068735
- Publication date Mar 8, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY
- Publication number 20170365346
- Publication date Dec 21, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY
- Publication number 20170053703
- Publication date Feb 23, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20170011807
- Publication date Jan 12, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT
- Publication number 20160365849
- Publication date Dec 15, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Gary Peter Moscaluk
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED, HIGH VOLTAGE TOLERANT CIRCUITS IN FLASH PATH
- Publication number 20160365147
- Publication date Dec 15, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20160005475
- Publication date Jan 7, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20150294731
- Publication date Oct 15, 2015
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES
- Publication number 20140369136
- Publication date Dec 18, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20140301139
- Publication date Oct 9, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE TOLERANT ROW DRIVER
- Publication number 20130170292
- Publication date Jul 4, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Bogdan I. GEORGESCU
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY DEVICES AND SYSTEMS
- Publication number 20130141978
- Publication date Jun 6, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. HIROSE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20120188826
- Publication date Jul 26, 2012
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Architecture Having Two Independently Controlled Voltage Pumps
- Publication number 20100074028
- Publication date Mar 25, 2010
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Low power bandgap reference circuit with increased accuracy and red...
- Publication number 20070152740
- Publication date Jul 5, 2007
- Bogdan I. Georgescu
- G05 - CONTROLLING REGULATING
Information Patent Application
Architecture, method(s) and circuitry for low power memories
- Publication number 20020191470
- Publication date Dec 19, 2002
- Keith A. Ford
- G11 - INFORMATION STORAGE

Bogdan I. Georgescu

Person

Patents Grantslast 30 patents

High voltage architecture for non-volatile memory

Method to reduce program disturbs in non-volatile memory cells

Method to reduce program disturbs in non-volatile memory cells

Memory architecture having two independently controlled voltage pumps

Memory architecture having two independently controlled voltage pumps

Method to reduce program disturbs in non-volatile memory cells

High voltage architecture for non-volatile memory

Negative high voltage hot switching circuit

High speed, high voltage tolerant circuits in flash path

Method to reduce program disturbs in non-volatile memory cells

Systems and methods for providing high voltage to memory devices

Method to reduce program disturbs in non-volatile memory cells

Flash memory devices and systems

Systems and methods for providing high voltage to memory devices

Method to reduce program disturbs in non-volatile memory cells

High voltage tolerant row driver

Flash memory devices and systems

Memory architecture having two independently controlled voltage pumps

Memory architecture having two independently controlled voltage pumps

Memory architecture having a reference current generator that provi...

Low power Bandgap reference circuit with increased accuracy and red...

Method and circuit for high speed transmission gate logic

Architecture, method(s) and circuitry for low power memories

Block redundancy in ultra low power memory circuits

Architecture, method (s) and circuitry for low power memories

Block redundancy in ultra low power memory circuits

Architecture, method(s) and circuitry for low power memories

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR TESTING A NON-VOLATILE MEMORY

HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY

HIGH VOLTAGE ARCHITECTURE FOR NON-VOLATILE MEMORY

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

NEGATIVE HIGH VOLTAGE HOT SWITCHING CIRCUIT

HIGH SPEED, HIGH VOLTAGE TOLERANT CIRCUITS IN FLASH PATH

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

HIGH VOLTAGE TOLERANT ROW DRIVER

FLASH MEMORY DEVICES AND SYSTEMS

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Memory Architecture Having Two Independently Controlled Voltage Pumps

Low power bandgap reference circuit with increased accuracy and red...

Architecture, method(s) and circuitry for low power memories