Brian D. Johnson

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Modular manufacture, delivery, and assembly of nuclear reactor buil...
- Patent number 11,746,550
- Issue date Sep 5, 2023
- TerraPower, LLC.
- Derek Bass
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Grant
Nuclear fuel assembly with multi-pitch wire wrap
- Patent number 11,725,411
- Issue date Aug 15, 2023
- TerraPower, LLC.
- Brian C Johnson
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Grant
Nuclear fuel assembly design
- Patent number 9,721,678
- Issue date Aug 1, 2017
- TerraPower, LLC.
- Jesse R. Cheatham
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Grant
Passive reactivity control apparatus
- Patent number 9,362,010
- Issue date Jun 7, 2016
- TerraPower, LLC.
- Jesse R. Cheatham
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multiple data rate memory interface architecture
- Patent number 9,224,438
- Issue date Dec 29, 2015
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 9,094,014
- Issue date Jul 28, 2015
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,732,646
- Issue date May 20, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance memory interface circuit architecture
- Patent number 8,593,195
- Issue date Nov 26, 2013
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate memory interface architecture
- Patent number 8,487,651
- Issue date Jul 16, 2013
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,407,649
- Issue date Mar 26, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 8,305,121
- Issue date Nov 6, 2012
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 8,201,129
- Issue date Jun 12, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple data rate memory interface architecture
- Patent number 7,994,816
- Issue date Aug 9, 2011
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,969,215
- Issue date Jun 28, 2011
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Passgate structures for use in low-voltage applications
- Patent number 7,800,405
- Issue date Sep 21, 2010
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLD architecture for flexible placement of IP function blocks
- Patent number 7,584,447
- Issue date Sep 1, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Passgate structures for use in low-voltage applications
- Patent number 7,557,608
- Issue date Jul 7, 2009
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,535,275
- Issue date May 19, 2009
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple data rate memory interface architecture
- Patent number 7,504,855
- Issue date Mar 17, 2009
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft core control of dedicated memory interface hardware in a progr...
- Patent number 7,323,903
- Issue date Jan 29, 2008
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
I/O configuration and reconfiguration trigger through testing inter...
- Patent number 7,287,189
- Issue date Oct 23, 2007
- Altera Corporation
- Brian D. Johnson
- G01 - MEASURING TESTING
Information Patent Grant
Precise phase shifting using a DLL controlled, multi-stage delay chain
- Patent number 7,234,069
- Issue date Jun 19, 2007
- Altera Corporation
- Brian D. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
High-performance memory interface circuit architecture
- Patent number 7,227,395
- Issue date Jun 5, 2007
- Altera Corporation
- Joseph Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for providing increased flexibility to input/output bank...
- Patent number 7,196,542
- Issue date Mar 27, 2007
- Altera Corporation
- Andy Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiple data rate memory interface architecture
- Patent number 7,176,714
- Issue date Feb 13, 2007
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft core control of dedicated memory interface hardware in a progr...
- Patent number 7,123,051
- Issue date Oct 17, 2006
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Passage structures for use in low-voltage applications
- Patent number 7,119,574
- Issue date Oct 10, 2006
- Altera Corporation
- Andy L Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for designing PLD architectures for flexible placement of I...
- Patent number 7,058,920
- Issue date Jun 6, 2006
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing architecture for a programmable logic device
- Patent number 6,970,014
- Issue date Nov 29, 2005
- Altera Corporation
- David M. Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with redundant circuitry
- Patent number 6,965,249
- Issue date Nov 15, 2005
- Altera Corporation
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR BUIL...
- Publication number 20240309665
- Publication date Sep 19, 2024
- TerraPower, LLC
- Derek Bass
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
NUCLEAR FUEL ASSEMBLY WITH MULTI-PITCH WIRE WRAP
- Publication number 20230323695
- Publication date Oct 12, 2023
- TerraPower, LLC
- Brian C Johnson
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR CORE...
- Publication number 20220051811
- Publication date Feb 17, 2022
- TerraPower, LLC
- Derek Bass
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR BUIL...
- Publication number 20220049516
- Publication date Feb 17, 2022
- TerraPower, LLC
- Derek Bass
- E04 - BUILDING
Information Patent Application
CONTAINMENT STRUCTURE AND ARRANGEMENT FOR NUCLEAR REACTOR
- Publication number 20220051815
- Publication date Feb 17, 2022
- TerraPower, LLC
- Brian C. Johnson
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
NUCLEAR FUEL ASSEMBLY WITH MULTI-PITCH WIRE WRAP
- Publication number 20220051812
- Publication date Feb 17, 2022
- TerraPower, LLC
- Brian C. Johnson
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
GAS-COOLED PRESSURE TUBE REACTOR
- Publication number 20180322968
- Publication date Nov 8, 2018
- TerraPower, LLC
- Jesse R. Cheatham
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
NUCLEAR FUEL ASSEMBLY DESIGN
- Publication number 20140341331
- Publication date Nov 20, 2014
- Jesse R. Cheatham
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20140210515
- Publication date Jul 31, 2014
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE
- Publication number 20140003115
- Publication date Jan 2, 2014
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20130214815
- Publication date Aug 22, 2013
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR CONTROLLING REACTIVITY IN A NUCLEAR FISSI...
- Publication number 20130177120
- Publication date Jul 11, 2013
- Searete LLC
- Jesse R. Cheatham
- G21 - NUCLEAR PHYSICS NUCLEAR ENGINEERING
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20120217998
- Publication date Aug 30, 2012
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE
- Publication number 20110260751
- Publication date Oct 27, 2011
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS
- Publication number 20090267645
- Publication date Oct 29, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS
- Publication number 20090224800
- Publication date Sep 10, 2009
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Passgate structures for use in low-voltage applications
- Publication number 20070008000
- Publication date Jan 11, 2007
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP functions blocks
- Publication number 20060033527
- Publication date Feb 16, 2006
- ALTERA CORPORATION, a corporation of Delaware
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Use of dangling partial lines for interfacing in a PLD
- Publication number 20040108871
- Publication date Jun 10, 2004
- Altera Corporation
- Brian D. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20030237071
- Publication date Dec 25, 2003
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with redundant circuitry
- Publication number 20030072185
- Publication date Apr 17, 2003
- Christopher Lane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLD architecture for flexible placement of IP function blocks
- Publication number 20020163356
- Publication date Nov 7, 2002
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Use of dangling partial lines for interfacing in a PLD
- Publication number 20020163358
- Publication date Nov 7, 2002
- Brian D. Johnson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device logic modules with shift register capabil...
- Publication number 20010048320
- Publication date Dec 6, 2001
- Altera Corporation
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY

Brian D. Johnson

Person

Patents Grantslast 30 patents

Modular manufacture, delivery, and assembly of nuclear reactor buil...

Nuclear fuel assembly with multi-pitch wire wrap

Nuclear fuel assembly design

Passive reactivity control apparatus

Multiple data rate memory interface architecture

PLD architecture for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

High performance memory interface circuit architecture

Multiple data rate memory interface architecture

PLD architecture for flexible placement of IP function blocks

High-performance memory interface circuit architecture

PLD architecture for flexible placement of IP function blocks

Multiple data rate memory interface architecture

High-performance memory interface circuit architecture

Passgate structures for use in low-voltage applications

PLD architecture for flexible placement of IP function blocks

Passgate structures for use in low-voltage applications

High-performance memory interface circuit architecture

Multiple data rate memory interface architecture

Soft core control of dedicated memory interface hardware in a progr...

I/O configuration and reconfiguration trigger through testing inter...

Precise phase shifting using a DLL controlled, multi-stage delay chain

High-performance memory interface circuit architecture

Techniques for providing increased flexibility to input/output bank...

Multiple data rate memory interface architecture

Soft core control of dedicated memory interface hardware in a progr...

Passage structures for use in low-voltage applications

Methods for designing PLD architectures for flexible placement of I...

Routing architecture for a programmable logic device

Programmable logic device with redundant circuitry

Patents Applicationslast 30 patents

MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR BUIL...

NUCLEAR FUEL ASSEMBLY WITH MULTI-PITCH WIRE WRAP

MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR CORE...

MODULAR MANUFACTURE, DELIVERY, AND ASSEMBLY OF NUCLEAR REACTOR BUIL...

CONTAINMENT STRUCTURE AND ARRANGEMENT FOR NUCLEAR REACTOR

NUCLEAR FUEL ASSEMBLY WITH MULTI-PITCH WIRE WRAP

GAS-COOLED PRESSURE TUBE REACTOR

NUCLEAR FUEL ASSEMBLY DESIGN

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

APPARATUS AND METHODS FOR CONTROLLING REACTIVITY IN A NUCLEAR FISSI...

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE

PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS

PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS

Passgate structures for use in low-voltage applications

PLD architecture for flexible placement of IP functions blocks

Use of dangling partial lines for interfacing in a PLD

PLD architecture for flexible placement of IP function blocks

Programmable logic device with redundant circuitry

PLD architecture for flexible placement of IP function blocks

Use of dangling partial lines for interfacing in a PLD

Programmable logic device logic modules with shift register capabil...