Bruce E. Whittaker

Person

San Juan Capistrano, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Recording relevant information in a GUI window of a panel dump brow...
- Patent number 7,793,229
- Issue date Sep 7, 2010
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic analysis of memory operations using panel dump file
- Patent number 7,401,261
- Issue date Jul 15, 2008
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Displaying abnormal and error conditions in system state analysis
- Patent number 7,171,593
- Issue date Jan 30, 2007
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control system for recreating of data output clock frequency which...
- Patent number 6,295,563
- Issue date Sep 25, 2001
- Unisys Corporation
- Bruce Ernest Whittaker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processor bus traffic optimization system for multi-level cache uti...
- Patent number 6,070,233
- Issue date May 30, 2000
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for compressing a plurality of contiguous addr...
- Patent number 6,070,166
- Issue date May 30, 2000
- Unisys Corporation
- Bruce E. Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear function generator method with counter for implementation of...
- Patent number 6,041,337
- Issue date Mar 21, 2000
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor bus traffic optimization system for multi-level cache uti...
- Patent number 6,000,015
- Issue date Dec 7, 1999
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for accessing coincident cache with a bit-sliced architecture
- Patent number 5,991,853
- Issue date Nov 23, 1999
- Unisys Corporation
- Bruce E. Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exponential functional relationship generator method and system for...
- Patent number 5,935,200
- Issue date Aug 10, 1999
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital device control method and system via linear function genera...
- Patent number 5,928,310
- Issue date Jul 27, 1999
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast write initialization method and system for loading channel ada...
- Patent number 5,889,959
- Issue date Mar 30, 1999
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor path emulation system providing fast readout and verifica...
- Patent number 5,850,513
- Issue date Dec 15, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi set cache structure having parity RAMs holding parity bits fo...
- Patent number 5,832,250
- Issue date Nov 3, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed initialization system for RAM devices using JTAG loop fo...
- Patent number 5,822,334
- Issue date Oct 13, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-arbitration system allowing look-around and bypass for signific...
- Patent number 5,790,813
- Issue date Aug 4, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Derived generation system for parity bits with bi-directional, cros...
- Patent number 5,768,299
- Issue date Jun 16, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast write initialization system for microcode RAM via data path ar...
- Patent number 5,737,567
- Issue date Apr 7, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart fill system for multiple cache network
- Patent number 5,729,712
- Issue date Mar 17, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting priority cache access operations with multiple level prio...
- Patent number 5,717,900
- Issue date Feb 10, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible, soft, random-like counter system for bus protocol waiting...
- Patent number 5,717,872
- Issue date Feb 10, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for adapting maintenance operations to JTAG and non-JTAG mod...
- Patent number 5,706,297
- Issue date Jan 6, 1998
- Unisys Corporation
- James Henry Jeppesen
- G01 - MEASURING TESTING
Information Patent Grant
System for fast read and verification of microcode RAM
- Patent number 5,706,424
- Issue date Jan 6, 1998
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for randomly selecting a cache set for cache fill...
- Patent number 5,701,431
- Issue date Dec 23, 1997
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for improved processor throughput with enhanced cache utiliz...
- Patent number 5,699,552
- Issue date Dec 16, 1997
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system and method for accessing a coincident cache wit...
- Patent number 5,689,680
- Issue date Nov 18, 1997
- Unisys Corp.
- Bruce E. Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable-depth, self-regulating cache queue flushing system
- Patent number 5,687,348
- Issue date Nov 11, 1997
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic reconfiguration of multiple-way cache system allowing uni...
- Patent number 5,666,513
- Issue date Sep 9, 1997
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Invalidation queue with "bit-sliceability"
- Patent number 5,642,486
- Issue date Jun 24, 1997
- Unisys Corporation
- Bruce E. Whittaker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced computer operational system using auxiliary mini-cache for...
- Patent number 5,640,531
- Issue date Jun 17, 1997
- Unisys Corporation
- Bruce Ernest Whittaker
- G06 - COMPUTING CALCULATING COUNTING

Bruce E. Whittaker

Person

Patents Grantslast 30 patents

Recording relevant information in a GUI window of a panel dump brow...

Automatic analysis of memory operations using panel dump file

Displaying abnormal and error conditions in system state analysis

Control system for recreating of data output clock frequency which...

Processor bus traffic optimization system for multi-level cache uti...

Apparatus and method for compressing a plurality of contiguous addr...

Linear function generator method with counter for implementation of...

Processor bus traffic optimization system for multi-level cache uti...

Methods for accessing coincident cache with a bit-sliced architecture

Exponential functional relationship generator method and system for...

Digital device control method and system via linear function genera...

Fast write initialization method and system for loading channel ada...

Processor path emulation system providing fast readout and verifica...

Multi set cache structure having parity RAMs holding parity bits fo...

High speed initialization system for RAM devices using JTAG loop fo...

Pre-arbitration system allowing look-around and bypass for signific...

Derived generation system for parity bits with bi-directional, cros...

Fast write initialization system for microcode RAM via data path ar...

Smart fill system for multiple cache network

Adjusting priority cache access operations with multiple level prio...

Flexible, soft, random-like counter system for bus protocol waiting...

System for adapting maintenance operations to JTAG and non-JTAG mod...

System for fast read and verification of microcode RAM

Method and system for randomly selecting a cache set for cache fill...

System for improved processor throughput with enhanced cache utiliz...

Cache memory system and method for accessing a coincident cache wit...

Variable-depth, self-regulating cache queue flushing system

Automatic reconfiguration of multiple-way cache system allowing uni...

Invalidation queue with "bit-sliceability"

Enhanced computer operational system using auxiliary mini-cache for...