Bruce Querbach

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Technologies for performing macro operations in memory
- Patent number 11,620,358
- Issue date Apr 4, 2023
- Intel Corporation
- Chetan Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell including multi-level sensing
- Patent number 11,264,094
- Issue date Mar 1, 2022
- Intel Corporation
- Bruce Querbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technologies for providing adaptive memory media management
- Patent number 11,182,158
- Issue date Nov 23, 2021
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having embedded non-volatile random access memory to supp...
- Patent number 11,074,151
- Issue date Jul 27, 2021
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure boot processor with embedded NVRAM
- Patent number 10,878,100
- Issue date Dec 29, 2020
- Intel Corporation
- Christopher Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Booting a computing system using embedded non-volatile memory
- Patent number 10,691,466
- Issue date Jun 23, 2020
- Intel Corporation
- Christopher Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended platform with additional memory module slots per CPU socke...
- Patent number 10,599,592
- Issue date Mar 24, 2020
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended platform with additional memory module slots per CPU socket
- Patent number 10,242,717
- Issue date Mar 26, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended platform with additional memory module slots per CPU socke...
- Patent number 10,216,657
- Issue date Feb 26, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test, validation, and debug architecture
- Patent number 10,198,333
- Issue date Feb 5, 2019
- Intel Corporation
- Mark B. Trobough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting multiple memory types in a memory slot
- Patent number 10,163,508
- Issue date Dec 25, 2018
- Intel Corporation
- Woojong Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective performance level modes of operation in a non-volatile me...
- Patent number 10,163,502
- Issue date Dec 25, 2018
- Intel Corporation
- Christopher F. Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power and area efficient memory receiver
- Patent number 10,014,036
- Issue date Jul 3, 2018
- Intel Corporation
- Kuan Zhou
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit reliability assessment apparatus and method
- Patent number 9,977,075
- Issue date May 22, 2018
- Intel Corporation
- Christopher F. Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller-controlled refresh abort
- Patent number 9,953,694
- Issue date Apr 24, 2018
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,922,725
- Issue date Mar 20, 2018
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory refresh operation with page open
- Patent number 9,824,743
- Issue date Nov 21, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended platform with additional memory module slots per CPU socket
- Patent number 9,818,457
- Issue date Nov 14, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Determination of demarcation voltage for managing drift in non-vola...
- Patent number 9,691,492
- Issue date Jun 27, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory refresh operation with page open
- Patent number 9,659,626
- Issue date May 23, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,564,245
- Issue date Feb 7, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit defect detection and repair
- Patent number 9,548,137
- Issue date Jan 17, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Robust memory link testing using memory controller
- Patent number 8,868,992
- Issue date Oct 21, 2014
- Intel Corporation
- Bryan L. Spry
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage margining with a low power, high speed, input offset cancel...
- Patent number 7,501,863
- Issue date Mar 10, 2009
- Intel Corporation
- Bruce Querbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Regulating a timing between a strobe signal and a data signal
- Patent number 7,480,360
- Issue date Jan 20, 2009
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for validating AC I/O loopback tests using...
- Patent number 7,228,515
- Issue date Jun 5, 2007
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic self test of an integrated circuit component via AC I/O l...
- Patent number 7,139,957
- Issue date Nov 21, 2006
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Push button mode automatic pattern switching for interconnect built...
- Patent number 6,826,100
- Issue date Nov 30, 2004
- Intel Corporation
- David G. Ellis
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNOLOGIES FOR PROVIDING ADAPTIVE MEMORY MEDIA MANAGEMENT
- Publication number 20190272173
- Publication date Sep 5, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY
- Publication number 20190266219
- Publication date Aug 29, 2019
- Intel Corporation
- Chetan Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...
- Publication number 20190258594
- Publication date Aug 22, 2019
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PERFORMING TENSOR OPERATIONS IN MEMORY
- Publication number 20190227750
- Publication date Jul 25, 2019
- Intel Corporation
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE PERFORMANCE LEVEL MODES OF OPERATION IN A NON-VOLATILE ME...
- Publication number 20190122729
- Publication date Apr 25, 2019
- Intel Corporation
- Christopher F. CONNOR
- G11 - INFORMATION STORAGE
Information Patent Application
SECURE BOOT PROCESSOR WITH EMBEDDED NVRAM
- Publication number 20190050573
- Publication date Feb 14, 2019
- Intel Corporation
- Christopher CONNOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-HEALING IN A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY
- Publication number 20190042351
- Publication date Feb 7, 2019
- Intel Corporation
- Christopher CONNOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL INCLUDING MULTI-LEVEL SENSING
- Publication number 20190043570
- Publication date Feb 7, 2019
- Intel Corporation
- Bruce Querbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BOOTING A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY
- Publication number 20190042275
- Publication date Feb 7, 2019
- Intel Corporation
- Christopher CONNOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING EMBEDDED NON-VOLATILE RANDOM ACCESS MEMORY TO SUPP...
- Publication number 20190042383
- Publication date Feb 7, 2019
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER AND AREA EFFICIENT MEMORY RECEIVER
- Publication number 20180190331
- Publication date Jul 5, 2018
- Intel Corporation
- Kuan Zhou
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE PERFORMANCE LEVEL MODES OF OPERATION IN A NON-VOLATILE ME...
- Publication number 20180190350
- Publication date Jul 5, 2018
- Intel Corporation
- Christopher F. CONNOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD
- Publication number 20180143242
- Publication date May 24, 2018
- Intel Corporation
- Christopher F. Connor
- G01 - MEASURING TESTING
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET
- Publication number 20180130505
- Publication date May 10, 2018
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...
- Publication number 20180095909
- Publication date Apr 5, 2018
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER-CONTROLLED REFRESH ABORT
- Publication number 20170352406
- Publication date Dec 7, 2017
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING MULTIPLE MEMORY TYPES IN A MEMORY SLOT
- Publication number 20170249991
- Publication date Aug 31, 2017
- Intel Corporation
- Woojong Han
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY REFRESH OPERATION WITH PAGE OPEN
- Publication number 20170236575
- Publication date Aug 17, 2017
- Intel Corporation
- Bruce QUERBACH
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD
- Publication number 20170160338
- Publication date Jun 8, 2017
- Intel Corporation
- Christopher F. Connor
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20170084351
- Publication date Mar 23, 2017
- Intel Corporation
- Bruce QUERBACH
- G11 - INFORMATION STORAGE
Information Patent Application
RACK SCALE ARCHITECTURE (RSA) AND SHARED MEMORY CONTROLLER (SMC) TE...
- Publication number 20160378151
- Publication date Dec 29, 2016
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20150187436
- Publication date Jul 2, 2015
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR
- Publication number 20150187439
- Publication date Jul 2, 2015
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST, VALIDATION, AND DEBUG ARCHITECTURE
- Publication number 20150127983
- Publication date May 7, 2015
- Intel Corporation
- Mark B. Trobough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER
- Publication number 20110161752
- Publication date Jun 30, 2011
- BRYAN L. SPRY
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage margining with a low power, high speed, input offset cancel...
- Publication number 20080231356
- Publication date Sep 25, 2008
- Bruce Querbach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Regulating a timing between a strobe signal and a data signal
- Publication number 20060265161
- Publication date Nov 23, 2006
- Bruce Querbach
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and apparatuses for validating AC I/O loopback tests using...
- Publication number 20050257185
- Publication date Nov 17, 2005
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic self test of an integrated circuit component via AC I/O l...
- Publication number 20040267479
- Publication date Dec 30, 2004
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pre-announce signaling for interconnect built-in self test
- Publication number 20040117708
- Publication date Jun 17, 2004
- David G. Ellis
- G06 - COMPUTING CALCULATING COUNTING

Bruce Querbach

Person

Patents Grantslast 30 patents

Technologies for performing macro operations in memory

Memory cell including multi-level sensing

Technologies for providing adaptive memory media management

Processor having embedded non-volatile random access memory to supp...

Secure boot processor with embedded NVRAM

Booting a computing system using embedded non-volatile memory

Extended platform with additional memory module slots per CPU socke...

Extended platform with additional memory module slots per CPU socket

Extended platform with additional memory module slots per CPU socke...

Test, validation, and debug architecture

Supporting multiple memory types in a memory slot

Selective performance level modes of operation in a non-volatile me...

Low power and area efficient memory receiver

Integrated circuit reliability assessment apparatus and method

Memory controller-controlled refresh abort

Integrated circuit defect detection and repair

Memory refresh operation with page open

Extended platform with additional memory module slots per CPU socket

Determination of demarcation voltage for managing drift in non-vola...

Memory refresh operation with page open

Integrated circuit defect detection and repair

Integrated circuit defect detection and repair

Robust memory link testing using memory controller

Voltage margining with a low power, high speed, input offset cancel...

Regulating a timing between a strobe signal and a data signal

Methods and apparatuses for validating AC I/O loopback tests using...

Automatic self test of an integrated circuit component via AC I/O l...

Push button mode automatic pattern switching for interconnect built...

Patents Applicationslast 30 patents

TECHNOLOGIES FOR PROVIDING ADAPTIVE MEMORY MEDIA MANAGEMENT

TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...

TECHNOLOGIES FOR PERFORMING TENSOR OPERATIONS IN MEMORY

SELECTIVE PERFORMANCE LEVEL MODES OF OPERATION IN A NON-VOLATILE ME...

SECURE BOOT PROCESSOR WITH EMBEDDED NVRAM

SELF-HEALING IN A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY

MEMORY CELL INCLUDING MULTI-LEVEL SENSING

BOOTING A COMPUTING SYSTEM USING EMBEDDED NON-VOLATILE MEMORY

PROCESSOR HAVING EMBEDDED NON-VOLATILE RANDOM ACCESS MEMORY TO SUPP...

LOW POWER AND AREA EFFICIENT MEMORY RECEIVER

SELECTIVE PERFORMANCE LEVEL MODES OF OPERATION IN A NON-VOLATILE ME...

INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...

MEMORY CONTROLLER-CONTROLLED REFRESH ABORT

SUPPORTING MULTIPLE MEMORY TYPES IN A MEMORY SLOT

MEMORY REFRESH OPERATION WITH PAGE OPEN

INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

RACK SCALE ARCHITECTURE (RSA) AND SHARED MEMORY CONTROLLER (SMC) TE...

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR

TEST, VALIDATION, AND DEBUG ARCHITECTURE

ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER

Voltage margining with a low power, high speed, input offset cancel...

Regulating a timing between a strobe signal and a data signal

Methods and apparatuses for validating AC I/O loopback tests using...

Automatic self test of an integrated circuit component via AC I/O l...

Pre-announce signaling for interconnect built-in self test