Burnell G. West

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test systems and methods for integrated circuit devices
- Patent number 7,765,443
- Issue date Jul 27, 2010
- Credence Systems Corporation
- Ahmed Rashid Syed
- G01 - MEASURING TESTING
Information Patent Grant
Test and diagnosis of semiconductors
- Patent number 7,761,751
- Issue date Jul 20, 2010
- Credence Systems Corporation
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Scan stream sequencing for testing integrated circuits
- Patent number 7,454,678
- Issue date Nov 18, 2008
- Credence Systems Corporation
- Jamie S. Cullen
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced pin count test method and apparatus
- Patent number 7,336,066
- Issue date Feb 26, 2008
- Credence Systems Corporation
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Diagnostic process for automated test equipment
- Patent number 7,222,280
- Issue date May 22, 2007
- Credence Systems Corporation
- Burnell G. West
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-deterministic protocol packet testing
- Patent number 7,212,941
- Issue date May 1, 2007
- Credence Systems Corporation
- Angarai T. Sivaram
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tester system having a multi-purpose memory
- Patent number 7,171,598
- Issue date Jan 30, 2007
- Credence Systems Corporation
- Jamie S. Cullen
- G11 - INFORMATION STORAGE
Information Patent Grant
Test system algorithmic program generators
- Patent number 7,143,326
- Issue date Nov 28, 2006
- Credence Systems Corporation
- Daniel Fan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for distributing events in an event stream
- Patent number 7,113,886
- Issue date Sep 26, 2006
- Credence Systems Corporation
- Burnell G. West
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-jitter clock for test system
- Patent number 7,093,177
- Issue date Aug 15, 2006
- Schlumberger Technologies, Inc.
- Burnell G. West
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit testing with ring-connected test instrument modules
- Patent number 7,035,755
- Issue date Apr 25, 2006
- Credence Systems Corporation
- Michael F. Jones
- G01 - MEASURING TESTING
Information Patent Grant
Test system formatters configurable for multiple data rates
- Patent number 7,017,091
- Issue date Mar 21, 2006
- Credence Systems Corporation
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Pin electronics interface circuit
- Patent number 6,940,271
- Issue date Sep 6, 2005
- NPTest, Inc.
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Pin electronics interface circuit
- Patent number 6,937,006
- Issue date Aug 30, 2005
- Credence Systems Corporation
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for distributing events in an event stream
- Patent number 6,928,387
- Issue date Aug 9, 2005
- Credence Systems Corporation
- Burnell G. West
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for high speed IC test interface
- Patent number 6,859,902
- Issue date Feb 22, 2005
- Credence Systems Corporation
- Wajih Dalal
- G01 - MEASURING TESTING
Information Patent Grant
Scan stream sequencing for testing integrated circuits
- Patent number 6,748,564
- Issue date Jun 8, 2004
- NPTest, LLC
- Jamie S. Cullen
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge placement and jitter measurement for electronic elements
- Patent number 6,622,107
- Issue date Sep 16, 2003
- NPTest LLC
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Time-to-digital converter
- Patent number 6,501,706
- Issue date Dec 31, 2002
- Burnell G. West
- G04 - HOROLOGY
Information Patent Grant
Measuring signals in a tester system
- Patent number 6,285,963
- Issue date Sep 4, 2001
- Schlumberger Technologies, Inc.
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Tester having event generation circuit for acquiring waveform by su...
- Patent number 6,128,754
- Issue date Oct 3, 2000
- Schlumberger Technologies, Inc.
- Egbert Graeve
- G01 - MEASURING TESTING
Information Patent Grant
Measuring signals in a tester system
- Patent number 6,081,484
- Issue date Jun 27, 2000
- Schlumberger Technologies, Inc.
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Fast reprogrammable logic with active links between cells
- Patent number 6,025,736
- Issue date Feb 15, 2000
- Dynalogic
- Madhukar Vora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Providing test vectors with pattern chaining definition
- Patent number 6,014,764
- Issue date Jan 11, 2000
- Schlumberger Technologies Inc.
- Egbert Graeve
- G01 - MEASURING TESTING
Information Patent Grant
FPGA with conductors segmented by active repeaters
- Patent number 6,002,268
- Issue date Dec 14, 1999
- DynaChip Corporation
- Paul Takao Sasaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiCMOS reprogrammable logic
- Patent number 5,668,495
- Issue date Sep 16, 1997
- Dynachip Corporation
- Madhukar B. Vora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
BiCMOS multiplexers and crossbar switches
- Patent number 5,570,059
- Issue date Oct 29, 1996
- Dyna Logic Corporation
- Madhukar B. Vora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Event sequencer for automatic test equipment
- Patent number 5,477,139
- Issue date Dec 19, 1995
- Schlumberger Technologies, Inc.
- Burnell West
- G01 - MEASURING TESTING
Information Patent Grant
Test generation by environment emulation
- Patent number 5,475,624
- Issue date Dec 12, 1995
- Schlumberger Technologies, Inc.
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Grant
Driver circuits for IC tester
- Patent number 5,430,400
- Issue date Jul 4, 1995
- Schlumberger Technologies Inc.
- Richard F. Herlein
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Biphase vernier time code generator
- Publication number 20060129350
- Publication date Jun 15, 2006
- Burnell G. West
- G04 - HOROLOGY
Information Patent Application
Non-deterministic protocol packet testing
- Publication number 20060047461
- Publication date Mar 2, 2006
- A.T. Sivaram
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Scan stream sequencing for testing integrated circuits
- Publication number 20060005096
- Publication date Jan 5, 2006
- Jamie S. Cullen
- G01 - MEASURING TESTING
Information Patent Application
Reduced pin count test method and apparatus
- Publication number 20050258818
- Publication date Nov 24, 2005
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Automatic test system
- Publication number 20050222789
- Publication date Oct 6, 2005
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Pin electronics interface circuit
- Publication number 20050024041
- Publication date Feb 3, 2005
- NPTest, Inc., a Delaware corporation
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Scan stream sequencing for testing integrated circuits
- Publication number 20040255212
- Publication date Dec 16, 2004
- Jamie S. Cullen
- G01 - MEASURING TESTING
Information Patent Application
Very small pin count IC tester
- Publication number 20040187049
- Publication date Sep 23, 2004
- NPTEST, INC.
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Tester system having a multi-purpose memory
- Publication number 20040039977
- Publication date Feb 26, 2004
- Jamie S. Cullen
- G01 - MEASURING TESTING
Information Patent Application
Circuit and method for distributing events in an event stream
- Publication number 20030139899
- Publication date Jul 24, 2003
- Burnell G. West
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit testing with ring-connected test instrument modules
- Publication number 20030105607
- Publication date Jun 5, 2003
- Michael F. Jones
- G01 - MEASURING TESTING
Information Patent Application
Pin electronics interface circuit
- Publication number 20030057990
- Publication date Mar 27, 2003
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Test system formatters
- Publication number 20030033556
- Publication date Feb 13, 2003
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Low-jitter clock for test system
- Publication number 20030005360
- Publication date Jan 2, 2003
- Burnell G. West
- G01 - MEASURING TESTING
Information Patent Application
Test system algorithmic program generators
- Publication number 20020188902
- Publication date Dec 12, 2002
- Daniel Fan
- G01 - MEASURING TESTING

Burnell G. West

Person

Patents Grantslast 30 patents

Test systems and methods for integrated circuit devices

Test and diagnosis of semiconductors

Scan stream sequencing for testing integrated circuits

Reduced pin count test method and apparatus

Diagnostic process for automated test equipment

Non-deterministic protocol packet testing

Tester system having a multi-purpose memory

Test system algorithmic program generators

Circuit and method for distributing events in an event stream

Low-jitter clock for test system

Circuit testing with ring-connected test instrument modules

Test system formatters configurable for multiple data rates

Pin electronics interface circuit

Pin electronics interface circuit

Circuit and method for distributing events in an event stream

Method and apparatus for high speed IC test interface

Scan stream sequencing for testing integrated circuits

Edge placement and jitter measurement for electronic elements

Time-to-digital converter

Measuring signals in a tester system

Tester having event generation circuit for acquiring waveform by su...

Measuring signals in a tester system

Fast reprogrammable logic with active links between cells

Providing test vectors with pattern chaining definition

FPGA with conductors segmented by active repeaters

BiCMOS reprogrammable logic

BiCMOS multiplexers and crossbar switches

Event sequencer for automatic test equipment

Test generation by environment emulation

Driver circuits for IC tester

Patents Applicationslast 30 patents

Biphase vernier time code generator

Non-deterministic protocol packet testing

Scan stream sequencing for testing integrated circuits

Reduced pin count test method and apparatus

Automatic test system

Pin electronics interface circuit

Scan stream sequencing for testing integrated circuits

Very small pin count IC tester

Tester system having a multi-purpose memory

Circuit and method for distributing events in an event stream

Circuit testing with ring-connected test instrument modules

Pin electronics interface circuit

Test system formatters

Low-jitter clock for test system

Test system algorithmic program generators