Byung Hoon Ahn

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit leadframe and fabrication method therefor
- Patent number 8,536,688
- Issue date Sep 17, 2013
- Stats Chippac Ltd.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe and semiconductor package made using the leadframe
- Patent number 8,410,585
- Issue date Apr 2, 2013
- Amkor Technology, Inc.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with passive device integration
- Patent number 7,960,816
- Issue date Jun 14, 2011
- ST Assembly Test Services Ltd.
- Seng Guan Chow
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package system with down-set die pad and method...
- Patent number 7,833,840
- Issue date Nov 16, 2010
- Stats Chippac Ltd.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally enhanced stacked die package and fabrication method
- Patent number 7,205,651
- Issue date Apr 17, 2007
- ST Assembly Test Services Ltd.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Moisture resistant integrated circuit leadframe package
- Patent number 7,135,760
- Issue date Nov 14, 2006
- ST Assembly Test Services Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages and leadframe assemblies
- Patent number 7,091,596
- Issue date Aug 15, 2006
- ST Assembly Test Services Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit leadframe with ground plane
- Patent number 7,064,420
- Issue date Jun 20, 2006
- ST Assembly Test Services Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leadframe and semiconductor package made using the leadframe
- Patent number 7,042,068
- Issue date May 9, 2006
- Amkor Technology, Inc.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with passive device integration
- Patent number 7,005,325
- Issue date Feb 28, 2006
- ST Assembly Test Services Ltd.
- Seng Guan Chow
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for fabricating semiconductor packages, and leadframe assemb...
- Patent number 6,858,470
- Issue date Feb 22, 2005
- ST Assembly Test Services Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DIE TRANSFER METHOD AND APPARATUS FOR MULTI-CHIP MODULE
- Publication number 20250118589
- Publication date Apr 10, 2025
- Silicon Box, Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE TRANSFER METHOD AND APPARATUS
- Publication number 20250079204
- Publication date Mar 6, 2025
- Silicon Box, Ltd.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWN-SET DIE PAD
- Publication number 20080032456
- Publication date Feb 7, 2008
- STATS ChipPAC Ltd.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMALLY ENHANCED STACKED DIE PACKAGE AND FABRICATION METHOD
- Publication number 20070148821
- Publication date Jun 28, 2007
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION
- Publication number 20060197198
- Publication date Sep 7, 2006
- ST ASSEMBLY TEST SERVICES LTD.
- Seng Guan Chow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Leadframe and semiconductor package made using the leadframe
- Publication number 20060151858
- Publication date Jul 13, 2006
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit leadframe and fabrication method therefor
- Publication number 20050263861
- Publication date Dec 1, 2005
- STATS ChipPAC Ltd.
- Byung Hoon Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermally enhanced stacked die package and fabrication method
- Publication number 20050230800
- Publication date Oct 20, 2005
- ST ASSEMBLY TEST SERVICES LTD.
- Byung Tai Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with passive device integration
- Publication number 20050173783
- Publication date Aug 11, 2005
- ST ASSEMBLY TEST SERVICES LTD.
- Seng Guan Chow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Semiconductor packages and leadframe assemblies
- Publication number 20050087846
- Publication date Apr 28, 2005
- ST ASSEMBLY TEST SERVICE LTD.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Moisture resistant integrated circuit leadframe package
- Publication number 20040061205
- Publication date Apr 1, 2004
- ST ASSEMBLY TEST SERVICES LTD.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit leadframe with ground plane
- Publication number 20040061204
- Publication date Apr 1, 2004
- ST ASSEMBLY TEST SERVICES LTD.
- Byung Joon Han
- H01 - BASIC ELECTRIC ELEMENTS

Byung Hoon Ahn

Person

Patents Grantslast 30 patents

Integrated circuit leadframe and fabrication method therefor

Leadframe and semiconductor package made using the leadframe

Semiconductor package with passive device integration

Integrated circuit package system with down-set die pad and method...

Thermally enhanced stacked die package and fabrication method

Moisture resistant integrated circuit leadframe package

Semiconductor packages and leadframe assemblies

Integrated circuit leadframe with ground plane

Leadframe and semiconductor package made using the leadframe

Semiconductor package with passive device integration

Method for fabricating semiconductor packages, and leadframe assemb...

Patents Applicationslast 30 patents

DIE TRANSFER METHOD AND APPARATUS FOR MULTI-CHIP MODULE

DIE TRANSFER METHOD AND APPARATUS

INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DOWN-SET DIE PAD

THERMALLY ENHANCED STACKED DIE PACKAGE AND FABRICATION METHOD

SEMICONDUCTOR PACKAGE WITH PASSIVE DEVICE INTEGRATION

Leadframe and semiconductor package made using the leadframe

Integrated circuit leadframe and fabrication method therefor

Thermally enhanced stacked die package and fabrication method

Semiconductor package with passive device integration

Semiconductor packages and leadframe assemblies

Moisture resistant integrated circuit leadframe package

Integrated circuit leadframe with ground plane