Claims
- 1. A leadframe for a semiconductor package, comprising:
signal and ground leads; a ground plane; a frame paddle; supports connecting the signal and ground leads, ground plane, and frame paddle in at least two different layers; and at least one force release and stress relief structure incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
- 2. The leadframe of claim 1 wherein the force release and stress relief structure further comprises at least one slot formed in the ground plane substantially adjacent a support connected thereto.
- 3. The leadframe of claim 1 wherein the force release and stress relief structure further comprises at least one link of reduced transverse extent formed in the ground plane near at least one of the supports connected thereto.
- 4. The leadframe of claim 3 wherein the force release and stress relief link further comprises a structure selected from the group consisting of Z-links, W-links, necks, slim linkages, open rings, holes, and a combination thereof.
- 5. The leadframe of claim 1 wherein the force release and stress relief structure further comprises a region of narrowed transverse extent formed in a ground lead.
- 6. The leadframe of claim 5 wherein the region of narrowed transverse extent further comprises a box slot.
- 7. The leadframe of claim 1 wherein the force release and stress relief structure further comprises supports connected symmetrically to the ground plane on opposite sides thereof.
- 8. The leadframe of claim 7 wherein the supports further comprise downsets connected to the ground plane.
- 9. The leadframe of claim 1 wherein the ground plane further comprises a bonding ring.
- 10. The leadframe of claim 1 wherein the ground plane further comprises tabs.
- 11. A semiconductor package, comprising:
a leadframe having:
signal and ground leads; a ground plane connected to a plurality of the ground leads; a frame paddle; supports connecting the signal and ground leads, ground plane, and frame paddle in at least three different layers; and force release and stress relief structures incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein; a semiconductor die located on the frame paddle; an adhesive securing the semiconductor die to the frame paddle; at least one ground wire connected between the semiconductor die and the ground plane; at least one signal wire connected between the semiconductor die and at least one of the signal leads; and an encapsulating body formed substantially around the leadframe, wires, and semiconductor die.
- 12. The package of claim 11 wherein the force release and stress relief structures further comprise slots formed in the ground plane adjacent supports connected thereto.
- 13. The package of claim 11 wherein the force release and stress relief structures further comprise links of reduced transverse extent formed in the ground plane near the supports connected thereto.
- 14. The package of claim 13 wherein the force release and stress relief links further comprise structures selected from the group consisting of Z-links, W-links, necks, slim linkages, open rings, holes, and a combination thereof.
- 15. The package of claim 11 wherein the force release and stress relief structures further comprise regions of narrowed transverse extent formed in the ground leads.
- 16. The package of claim 15 wherein the regions of narrowed transverse extent further comprise box slots.
- 17. The package of claim 11 wherein the force release and stress relief structures further comprise supports connected symmetrically to the ground plane on opposite sides thereof.
- 18. The package of claim 17 wherein the supports further comprise downsets connected to the ground plane.
- 19. The package of claim 11 wherein the ground plane further comprises a bonding ring.
- 20. The package of claim 11 wherein the ground plane further comprises tabs.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims the benefit of U.S. Provisional Patent Application serial No. 60/415,330 filed Sep. 30, 2002, and the subject matter thereof is hereby incorporated herein by reference thereto.
[0002] The present application contains subject matter related to a co-pending U.S. Provisional Patent Application serial No. 60/415,227 filed Sep. 30, 2002, and the subject matter thereof is hereby incorporated herein by reference thereto.
[0003] The present application also contains subject matter related to a concurrently filed U.S. patent application by Byung Joon Han and Byung Hoon Ahn entitled “MOISTURE RESISTANT INTEGRATED CIRCUIT LEADFRAME PACKAGE”. This application is identified by docket number 27-005, and the subject matter thereof is hereby incorporated herein by reference thereto. This related patent application is assigned to ST Assembly Test Services Ltd.
Provisional Applications (1)
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Number |
Date |
Country |
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60415330 |
Sep 2002 |
US |