Claims
- 1. A leadframe for a semiconductor die, comprising:
signal leads; ground leads; and a die support holder for supporting the semiconductor die, the die support holder having opposite surfaces and side edges therebetween, the opposite die support holder surfaces being smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite die support holder surfaces such that the die extends beyond the side edges of the die support holder.
- 2. The leadframe of claim 1 further comprising a ground plane bonding structure supported at a predetermined position relative to the die support holder.
- 3. The leadframe of claim 2 further comprising a force release and stress relief structure formed in the ground plane bonding structure to free the ground plane bonding structure substantially from distortion and warpage resulting from residual mechanical stresses therein.
- 4. The leadframe of claim 3 wherein the force release and stress relief structure further comprises at least one corner D-ring opening formed in the ground plane bonding structure.
- 5. The leadframe of claim 3 wherein the force release and stress relief structure further comprises at least one bonding ring hole formed in the ground plane bonding structure.
- 6. A leadframe for a semiconductor die, comprising:
signal and ground leads; a ground plane connected to a plurality of the ground leads; a frame paddle for supporting the semiconductor die, the frame paddle having opposite surfaces and side edges therebetween, the opposite frame paddle surfaces being smaller in transverse extent than the semiconductor die for supporting the die on one of the opposite frame paddle surfaces such that the die extends beyond the side edges of the frame paddle; and supports connecting the signal and ground leads, ground plane, and frame paddle in at least three different layers.
- 7. The leadframe of claim 6 wherein the ground plane further comprises a ground plane bonding ring.
- 8. The leadframe of claim 7 further comprising force release and stress relief structures incorporated into the ground plane bonding ring to free the ground plane bonding ring substantially from distortion and warpage resulting from residual mechanical stresses therein.
- 9. The leadframe of claim 8 wherein the force release and stress relief structures further comprise corner D-ring openings formed in the ground plane bonding ring.
- 10. The leadframe of claim 8 wherein the force release and stress relief structures further comprise bonding ring holes formed in the ground plane bonding ring.
- 11. A semiconductor package, comprising:
a semiconductor die; a leadframe having a die support holder having opposite surfaces and side edges therebetween, the opposite die support holder surfaces being smaller in transverse extent than the semiconductor die, and the die being supported on one of the opposite die support holder surfaces and extending beyond the side edges of the die support holder; and an encapsulating body formed substantially around at least the semiconductor die and the die support holder surface on which the die is located, the encapsulating body being formed to leave the opposite die support holder surface unencapsulated.
- 12. The package of claim 11 further comprising signal leads, ground leads, and a ground plane bonding structure supported at predetermined positions relative to the die support holder.
- 13. The package of claim 12 further comprising a force release and stress relief structure formed in the ground plane bonding structure to free the ground plane bonding structure substantially from distortion and warpage resulting from residual mechanical stresses therein.
- 14. The package of claim 13 wherein the force release and stress relief structure further comprises at least one corner D-ring opening formed in the ground plane bonding structure.
- 15. The package of claim 13 wherein the force release and stress relief structure further comprises at least one bonding ring hole formed in the ground plane bonding structure.
- 16. A semiconductor package, comprising:
a semiconductor die; a leadframe having:
signal and ground leads; a ground plane connected to a plurality of the ground leads; a frame paddle having opposite surfaces and side edges therebetween, the opposite frame paddle surfaces being smaller in transverse extent than the semiconductor die, and the die being supported on one of the opposite frame paddle surfaces and extending beyond the side edges of the frame paddle; and supports connecting the signal and ground leads, ground plane, and frame paddle in at least three different layers; an adhesive securing the semiconductor die to the frame paddle; at least one ground wire connected between the semiconductor die and the ground plane; at least one signal wire connected between the semiconductor die and at least one of the signal leads; and an encapsulating body formed substantially around the leadframe, wires, semiconductor die, and the frame paddle surface on which the die is located, the encapsulating body being formed to leave the opposite frame paddle surface unencapsulated.
- 17. The package of claim 16 wherein the ground plane further comprises a ground plane bonding ring.
- 18. The package of claim 17 further comprising force release and stress relief structures incorporated into the ground plane bonding ring to free the ground plane bonding ring substantially from distortion and warpage resulting from residual mechanical stresses therein.
- 19. The package of claim 18 wherein the force release and stress relief structures further comprise corner D-ring openings formed in the ground plane bonding ring.
- 20. The package of claim 18 wherein the force release and stress relief structures further comprise bonding ring holes formed in the ground plane bonding ring.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims the benefit of U.S. Provisional Patent Application serial No. 60/415,227 filed Nov. 30, 2002, and the subject matter thereof is hereby incorporated herein by reference thereto.
[0002] The present application contains subject matter related to a co-pending U.S. Provisional Patent Application serial No. 60/415,330 filed Nov. 30, 2002, and the subject matter thereof is hereby incorporated herein by reference thereto.
[0003] The present application also contains subject matter related to a concurrently filed U.S. Patent Application by Byung Joon Han, Byung Hoon Ahn, and Zheng Zheng entitled “INTEGRATED CIRCUIT LEADFRAME WITH GROUND PLANE”. This application is identified by docket number 27-004, and the subject matter thereof is hereby incorporated herein by reference thereto. This related patent application is assigned to ST Assembly Test Services Ltd.
Provisional Applications (1)
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Number |
Date |
Country |
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60415227 |
Sep 2002 |
US |