Carlos Mazure-Espejo

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated semiconductor memory configuration with a buried plate e...
- Patent number 6,627,934
- Issue date Sep 30, 2003
- Infineon Technologies AG
- Günther Schindler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing an integrated semiconductor memory configuration
- Patent number 6,605,505
- Issue date Aug 12, 2003
- Siemens Aktiengesellschaft
- Frank Hintermaier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit with a sensor and non-volatile memory having a ferroelectri...
- Patent number 6,414,300
- Issue date Jul 2, 2002
- Infineon Technologies AG
- Carlos Mazure-Espejo
- G11 - INFORMATION STORAGE
Information Patent Grant
Layer configuration with a material layer and a diffusion barrier w...
- Patent number 6,337,239
- Issue date Jan 8, 2002
- Siemens Aktiengesellschaft
- Christine Dehm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Easy to manufacture integrated semiconductor memory configuration w...
- Patent number 6,316,802
- Issue date Nov 13, 2001
- Infineon Technologies AG
- Günther Schindler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing barrier-free semiconductor memory configurations
- Patent number 6,297,526
- Issue date Oct 2, 2001
- Siemens Aktiengesellschaft
- Frank Hintermaier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for the production of an integrated semiconductor memory con...
- Patent number 6,197,633
- Issue date Mar 6, 2001
- Infineon Technologies AG
- Günther Schindler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing barrier-free semiconductor memory configurations
- Patent number 6,168,988
- Issue date Jan 2, 2001
- Infineon Technologies, AG
- GG{umlaut over (u)}nther Schindler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing a ceramic layer
- Patent number 6,156,673
- Issue date Dec 5, 2000
- Infineon Technologies AG
- Frank Hintermaier
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Production process for a capacitor electrode formed of a platinum m...
- Patent number 6,136,659
- Issue date Oct 24, 2000
- Infineon Technologies AG
- Gunther Schindler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for producing a ceramic layer containing Bi
- Patent number 6,126,998
- Issue date Oct 3, 2000
- Siemens Aktiengesellschaft
- Frank Hintermaier
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of producing a barrier layer in a semiconductor body
- Patent number 6,100,187
- Issue date Aug 8, 2000
- Siemens Aktiengesellschaft
- Frank Hintermaier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory configuration with self-aligning non-integrated capacitor co...
- Patent number 6,097,050
- Issue date Aug 1, 2000
- Siemens Aktiengesellschaft
- Walter Hartner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric memory and method for preventing aging in a memory cell
- Patent number 6,091,625
- Issue date Jul 18, 2000
- Siemens Aktiengesellschaft
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor configuration with a protected barrier for a stacked...
- Patent number 6,043,529
- Issue date Mar 28, 2000
- Siemens Aktiengesellschaft
- Walter Hartner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing a noble metal-containing structure on a substr...
- Patent number 6,037,256
- Issue date Mar 14, 2000
- Siemens Aktiengesellschaft
- Volker Weinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for a raised capacitor electrode
- Patent number 6,004,856
- Issue date Dec 21, 1999
- Siemens Aktiengesellschaft
- Carlos Mazure-Espejo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing wells for CMOS transistor circuits separat...
- Patent number 4,906,585
- Issue date Mar 6, 1990
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for making neighboring wells for VLS1 CMOS components
- Patent number 4,803,179
- Issue date Feb 7, 1989
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming retrograde twin wells by outdiffusion of impurity ions in e...
- Patent number 4,761,384
- Issue date Aug 2, 1988
- Siemens Aktiengesellschaft
- Franz Neppl
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Process for producing an integrated semiconductor memory configuration
- Publication number 20010039106
- Publication date Nov 8, 2001
- Siemens Aktiengesellschaft
- Frank Hintermaier
- H01 - BASIC ELECTRIC ELEMENTS

Carlos Mazure-Espejo

Person

Patents Grantslast 30 patents

Integrated semiconductor memory configuration with a buried plate e...

Process for producing an integrated semiconductor memory configuration

Circuit with a sensor and non-volatile memory having a ferroelectri...

Layer configuration with a material layer and a diffusion barrier w...

Easy to manufacture integrated semiconductor memory configuration w...

Process for producing barrier-free semiconductor memory configurations

Method for the production of an integrated semiconductor memory con...

Method for producing barrier-free semiconductor memory configurations

Process for producing a ceramic layer

Production process for a capacitor electrode formed of a platinum m...

Process for producing a ceramic layer containing Bi

Method of producing a barrier layer in a semiconductor body

Memory configuration with self-aligning non-integrated capacitor co...

Ferroelectric memory and method for preventing aging in a memory cell

Semiconductor configuration with a protected barrier for a stacked...

Method for producing a noble metal-containing structure on a substr...

Manufacturing process for a raised capacitor electrode

Method for manufacturing wells for CMOS transistor circuits separat...

Methods for making neighboring wells for VLS1 CMOS components

Forming retrograde twin wells by outdiffusion of impurity ions in e...

Patents Applicationslast 30 patents

Process for producing an integrated semiconductor memory configuration