Carlos Mazure

Person

St. Nazire les Eymes, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Pseudo-inverter circuit with multiple independent gate transistors
- Patent number 9,496,877
- Issue date Nov 15, 2016
- Soitec
- Carlos Mazure
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device having a contact between semiconductor regions through a bur...
- Patent number 9,490,264
- Issue date Nov 8, 2016
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory having staggered sense amplifiers associated w...
- Patent number 9,159,400
- Issue date Oct 13, 2015
- Soitec
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for manufacturing a semiconductor substrate
- Patent number 9,035,474
- Issue date May 19, 2015
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded semiconductor structures and method of forming same
- Patent number 8,987,114
- Issue date Mar 24, 2015
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate having a charged zone in an insulating buried layer
- Patent number 8,735,946
- Issue date May 27, 2014
- Soitec
- Mohamad A Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell on SeOI having a second control gate buried under...
- Patent number 8,664,712
- Issue date Mar 4, 2014
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit on SeOI
- Patent number 8,654,602
- Issue date Feb 18, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-layer structures and process for fabricating semiconductor de...
- Patent number 8,652,887
- Issue date Feb 18, 2014
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,625,374
- Issue date Jan 7, 2014
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for transferring a monocrystalline semiconductor layer onto...
- Patent number 8,603,896
- Issue date Dec 10, 2013
- Soitec
- Gweltaz Gaudin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM-type memory cell
- Patent number 8,575,697
- Issue date Nov 5, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Substrate having a charged zone in an insulating buried layer
- Patent number 8,535,996
- Issue date Sep 17, 2013
- Soitec
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data-path cell on an SeOI substrate with a back control gate beneat...
- Patent number 8,508,289
- Issue date Aug 13, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully depleted SOI device with buried doped layer
- Patent number 8,492,844
- Issue date Jul 23, 2013
- Soitec
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Relaxation of strained layers
- Patent number 8,481,408
- Issue date Jul 9, 2013
- Soitec
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device comprising a field-effect transistor in a silicon-on-insulator
- Patent number 8,455,938
- Issue date Jun 4, 2013
- Soitec
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data-path cell on an SeOI substrate with a back control gate beneat...
- Patent number 8,432,216
- Issue date Apr 30, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrays of transistors with back control gates buried beneath the in...
- Patent number 8,384,425
- Issue date Feb 26, 2013
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano-sense amplifier
- Patent number 8,358,552
- Issue date Jan 22, 2013
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices and methods for comparing data in a content-addressable memory
- Patent number 8,325,506
- Issue date Dec 4, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for manufacturing multilayer wafers with trench structures
- Patent number 8,309,426
- Issue date Nov 13, 2012
- Soitec
- Konstantin Bourdelle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell with a channel buried beneath a dielectric layer
- Patent number 8,304,833
- Issue date Nov 6, 2012
- Soitec
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DRAM memory cell having a vertical bipolar injector
- Patent number 8,305,803
- Issue date Nov 6, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of fabricating a back-illuminated image sensor
- Patent number 8,241,942
- Issue date Aug 14, 2012
- Soitec
- Konstantin Bourdelle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-inverter circuit on SeOI
- Patent number 8,223,582
- Issue date Jul 17, 2012
- Soitec
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Grant
Forming structures that include a relaxed or pseudo-relaxed layer o...
- Patent number 8,173,512
- Issue date May 8, 2012
- Soitec
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures for relaxation of strained layers
- Patent number 8,048,693
- Issue date Nov 1, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Fabrice Letertre
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Low-cost double-structure substrates and methods for their manufacture
- Patent number 8,035,163
- Issue date Oct 11, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost substrates and method of forming such substrates
- Patent number 8,013,417
- Issue date Sep 6, 2011
- S.O.I.T.ec Silicon on Insulator Technologies
- Bich-Yen Nguyen
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
FINFET WITH BACK-GATE
- Publication number 20160020326
- Publication date Jan 21, 2016
- SOITEC
- Carlos MAZURE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPLEMENTARY FET INJECTION FOR A FLOATING BODY CELL
- Publication number 20150145049
- Publication date May 28, 2015
- SOITEC
- Franz Hoffman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS
- Publication number 20140225648
- Publication date Aug 14, 2014
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
- Publication number 20140225182
- Publication date Aug 14, 2014
- SOITEC
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
- Publication number 20140015023
- Publication date Jan 16, 2014
- SOITEC
- Frederic Allibert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANO-SENSE AMPLIFIER
- Publication number 20130100749
- Publication date Apr 25, 2013
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO...
- Publication number 20130029474
- Publication date Jan 31, 2013
- SOITEC
- Gweltaz Gaudin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME
- Publication number 20130015442
- Publication date Jan 17, 2013
- SOITEC
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeOI
- Publication number 20120250444
- Publication date Oct 4, 2012
- SOITEC
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...
- Publication number 20120243360
- Publication date Sep 27, 2012
- Richard Ferrant
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...
- Publication number 20120231606
- Publication date Sep 13, 2012
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION OF STRAINED LAYERS
- Publication number 20120214291
- Publication date Aug 23, 2012
- SOITEC
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER
- Publication number 20120181609
- Publication date Jul 19, 2012
- Gerhard Enders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES
- Publication number 20110294277
- Publication date Dec 1, 2011
- Konstantin Bourdelle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR
- Publication number 20110287571
- Publication date Nov 24, 2011
- S. O. I. Tec Silicon on Insulator Technologies
- Konstantin Bourdelle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR
- Publication number 20110260233
- Publication date Oct 27, 2011
- Bich-Yen Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110241157
- Publication date Oct 6, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-INVERTER CIRCUIT ON SeO1
- Publication number 20110242926
- Publication date Oct 6, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM-TYPE MEMORY CELL
- Publication number 20110233675
- Publication date Sep 29, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
NANO-SENSE AMPLIFIER
- Publication number 20110222361
- Publication date Sep 15, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...
- Publication number 20110217825
- Publication date Sep 8, 2011
- S.O.I.Tec Silicon on Insulator Technologies
- Bruno Ghyselen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...
- Publication number 20110215860
- Publication date Sep 8, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER
- Publication number 20110169087
- Publication date Jul 14, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR
- Publication number 20110170343
- Publication date Jul 14, 2011
- Carlos Mazure
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY
- Publication number 20110170327
- Publication date Jul 14, 2011
- Carlos Mazure
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BUR...
- Publication number 20110169090
- Publication date Jul 14, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RELAXATION OF STRAINED LAYERS
- Publication number 20110143522
- Publication date Jun 16, 2011
- Fabrice Letertre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...
- Publication number 20110133822
- Publication date Jun 9, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER...
- Publication number 20110134698
- Publication date Jun 9, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE IN...
- Publication number 20110133776
- Publication date Jun 9, 2011
- Carlos Mazure
- H01 - BASIC ELECTRIC ELEMENTS

Carlos Mazure

Person

Patents Grantslast 30 patents

Pseudo-inverter circuit with multiple independent gate transistors

Device having a contact between semiconductor regions through a bur...

Semiconductor memory having staggered sense amplifiers associated w...

Method for manufacturing a semiconductor substrate

Bonded semiconductor structures and method of forming same

Substrate having a charged zone in an insulating buried layer

Flash memory cell on SeOI having a second control gate buried under...

Pseudo-inverter circuit on SeOI

Multi-layer structures and process for fabricating semiconductor de...

Nano-sense amplifier

Method for transferring a monocrystalline semiconductor layer onto...

SRAM-type memory cell

Substrate having a charged zone in an insulating buried layer

Data-path cell on an SeOI substrate with a back control gate beneat...

Fully depleted SOI device with buried doped layer

Relaxation of strained layers

Device comprising a field-effect transistor in a silicon-on-insulator

Data-path cell on an SeOI substrate with a back control gate beneat...

Arrays of transistors with back control gates buried beneath the in...

Nano-sense amplifier

Devices and methods for comparing data in a content-addressable memory

Methods for manufacturing multilayer wafers with trench structures

Memory cell with a channel buried beneath a dielectric layer

DRAM memory cell having a vertical bipolar injector

Method of fabricating a back-illuminated image sensor

Pseudo-inverter circuit on SeOI

Forming structures that include a relaxed or pseudo-relaxed layer o...

Methods and structures for relaxation of strained layers

Low-cost double-structure substrates and methods for their manufacture

Low cost substrates and method of forming such substrates

Patents Applicationslast 30 patents

FINFET WITH BACK-GATE

COMPLEMENTARY FET INJECTION FOR A FLOATING BODY CELL

PSEUDO-INVERTER CIRCUIT WITH MULTIPLE INDEPENDENT GATE TRANSISTORS

SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER

SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER

NANO-SENSE AMPLIFIER

METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER ONTO...

BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME

PSEUDO-INVERTER CIRCUIT ON SeOI

SEMICONDUCTOR MEMORY HAVING STAGGERED SENSE AMPLIFIERS ASSOCIATED W...

MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DE...

RELAXATION OF STRAINED LAYERS

FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER

METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES

METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR

DEVICE COMPRISING A FIELD-EFFECT TRANSISTOR IN A SILICON-ON-INSULATOR

METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

PSEUDO-INVERTER CIRCUIT ON SeO1

SRAM-TYPE MEMORY CELL

NANO-SENSE AMPLIFIER

FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER O...

DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...

MEMORY CELL WITH A CHANNEL BURIED BENEATH A DIELECTRIC LAYER

DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR

DEVICES AND METHODS FOR COMPARING DATA IN A CONTENT-ADDRESSABLE MEMORY

DEVICE HAVING A CONTACT BETWEEN SEMICONDUCTOR REGIONS THROUGH A BUR...

RELAXATION OF STRAINED LAYERS

DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEAT...

FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER...

ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE IN...