Chan-Liang Wu

Person

Tainan, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device having alignment mark
- Patent number 8,912,671
- Issue date Dec 16, 2014
- Himax Technologies Limited
- Po-Yang Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of resistor matching in analog integrated circuit layout
- Patent number 8,751,987
- Issue date Jun 10, 2014
- Oryx Holdings Pty Ltd.
- Tsung-Yi Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floorplanning method for an analog integrated circuit layout
- Patent number 8,726,214
- Issue date May 13, 2014
- NCKU Research and Development Foundation
- Tsung-Yi Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for preventing leakage of a semiconductor device
- Patent number 7,598,585
- Issue date Oct 6, 2009
- Himax Technologies Limited
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with a reduced pad bump area and the manufacturi...
- Patent number 7,541,274
- Issue date Jun 2, 2009
- Himax Technologies Limited
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Triple operation voltage device
- Patent number 7,514,761
- Issue date Apr 7, 2009
- Himax Technologies, Inc.
- Tz-Ian Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for leakage prevention of a high voltage device
- Patent number 7,388,266
- Issue date Jun 17, 2008
- Himax Technologies Limited
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20140339714
- Publication date Nov 20, 2014
- HIMAX SEMICONDUCTOR, INC.
- Po-Yang Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLOORPLANNING METHOD FOR AN ANALOG INTEGRATED CIRCUIT LAYOUT
- Publication number 20130283226
- Publication date Oct 24, 2013
- HIMAX TECHNOLOGIES LIMITED
- Tsung-Yi Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF RESISTOR MATCHING IN ANALOG INTEGRATED CIRCUIT LAYOUT
- Publication number 20130145332
- Publication date Jun 6, 2013
- HIMAX TECHNOLOGIES LIMITED
- Tsung-Yi Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D-IC Verification Method
- Publication number 20100257495
- Publication date Oct 7, 2010
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for Preventing Leakage of a Semiconductor Device
- Publication number 20090309169
- Publication date Dec 17, 2009
- HIMAX TECHNOLOGIES LIMITED
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH A REDUCED PAD BUMP AREA AND THE MANUFACTURI...
- Publication number 20080093737
- Publication date Apr 24, 2008
- HIMAX TECHNOLOGIES LIMITED
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Triple operation voltage device
- Publication number 20070102782
- Publication date May 10, 2007
- Tz-Ian Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
A STRUCTURE FOR PREVENTING LEAKAGE OF A SEMICONDUCTOR DEVICE
- Publication number 20060255430
- Publication date Nov 16, 2006
- HIMAX TECHNOLOGIES, INC.
- CHAN-LIANG WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for leakage prevention of a high voltage device
- Publication number 20060255429
- Publication date Nov 16, 2006
- HIMAX TECHNOLOGIES, INC.
- Chan-Liang Wu
- H01 - BASIC ELECTRIC ELEMENTS

Chan-Liang Wu

Person

Patents Grantslast 30 patents

Semiconductor device having alignment mark

Method of resistor matching in analog integrated circuit layout

Floorplanning method for an analog integrated circuit layout

Structure for preventing leakage of a semiconductor device

Integrated circuit with a reduced pad bump area and the manufacturi...

Triple operation voltage device

Structure for leakage prevention of a high voltage device

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE

FLOORPLANNING METHOD FOR AN ANALOG INTEGRATED CIRCUIT LAYOUT

METHOD OF RESISTOR MATCHING IN ANALOG INTEGRATED CIRCUIT LAYOUT

3D-IC Verification Method

Structure for Preventing Leakage of a Semiconductor Device

INTEGRATED CIRCUIT WITH A REDUCED PAD BUMP AREA AND THE MANUFACTURI...

Triple operation voltage device

A STRUCTURE FOR PREVENTING LEAKAGE OF A SEMICONDUCTOR DEVICE

Structure for leakage prevention of a high voltage device