1. Field of the Invention
The present invention generally relates to integrated circuit (IC) verification, and more particularly to a three-dimensional integrated circuit (3D-IC) verification method adaptable to two-dimensional (2D) electronic design automation (EDA) tools.
2. Description of the Prior Art
As modern electronic systems become more complex, system on chip (SOC) techniques are often used to integrate all electronic components of the electronic system into a single chip. However, it is at times not feasible to construct the electronic system using SOC techniques due to a variety of incompatible process techniques involved.
The three-dimensional integrated circuit (3D-IC) technique, therefore, has shown promise as a technique to construct an integrated circuit with two or more chips integrated vertically and horizontally, even with process-incompatible chips. The 3D IC becomes more popular when the through-silicon via (TSV) technique is applied to electrically connect chips vertically by way of via.
The complexities of modern ICs demand electronic design automation (EDA) tools, such as IC layout editors and IC verification tools (e.g., design rule check (DRC) and layout vs. schematic (LVS)), to design and verify the functions of the ICs before being actually manufactured. As the 3D-IC technique is still new to the industry, no real 3D EDA tools have been developed at present. Conventional (two-dimensional, or 2D) EDA tools may be used, at best, to verify the individual chip or chips of the same level; however, the 2D EDA tools, unfortunately, cannot be used to verify the interconnections among the chips of different levels. The reason that the conventional 2D EDA tools cannot be used in verifying the 3D IC is that the electronic components of all the chips are indiscernible in the resultant drawing layer. Accordingly, the misplacement between the TSV 31 and the bump structure 32 exemplified in
For the reason that the conventional 2D EDA tools cannot be effectively used to verify the 3D IC or no real 3D-IC EDA tool has yet been developed, a need has arisen to propose a 3D-IC verification method that is capable of integrating with the conventional 2D EDA tools or is utilized alone to verify the 3D IC.
In view of the foregoing, it is an object of the present invention to provide a 3D-IC verification method, which may integrate with the conventional 2D EDA tool or work alone to provide capability of verifying 3D ICs. The integrated EDA tool can really verify the 3D ICs without resorting to a costly 3D EDA tool, if even existing.
According to one embodiment of the present invention, alignment mark(s), through-silicon via (TSV) and micro bump structure are defined and depicted on dummy layer(s) for each level of the 3D IC, followed by verifying chip(s), the alignment mark, the TSV and the micro bump structure for each level respectively. The dummy layers of all of the levels are extracted by streaming, and are then integrated according to the alignment marks. The integrated dummy layers of the 3D IC are verified vertically, and the connections between the TSV and the micro bump structure of different levels are then checked.
A flow diagram of a 3D-IC (three-dimensional integrated circuit) verification method according to one embodiment of the present invention is shown in
In step 51, at least one dummy layer is provided for each level of the 3D IC, and alignment mark or marks are defined and depicted on the dummy layer. Similarly, TSV and bump structure for each level are also depicted on the at least one dummy layer. In the embodiment, the alignment mark(s) and the TSV of the same level are depicted on the same dummy layer, while the bump structure of the same level are depicted on another dummy layer. As used herein, the term “TSV” means one or more TSVs, and the term “bump structure” means one or more bumps.
After the alignment-mark/TSV/bump dummy layers are provided in step 51, each level is then individually subjected to IC verification, such as design rule check (DRC) and layout vs. schematic (LVS) in step 52. The verification for each level may be performed using conventional (two-dimensional, or 2D) electronic design automation (EDA) tools, the associated descriptions of which are omitted herein for brevity.
Subsequently, in step 53, all electronic components except the dummy layers for each level of the 3D IC are streamed out respectively. As used herein, the term “stream out” means that the files of proprietary EDA tools are transformed from library database (with proprietary format) into a standard database file format, such as Graphic Data System II (GDSII, owned by Cadence Design Systems) or Open Artwork System Interchange Standard (OASIS, owned by SEMI). The transformed file (GDSII or OASIS) is a binary file that represents layout information such as geometry shapes and text labels, and provides cell and chip level physical and mask layout data ready for IC fabrication in IC foundries. In the depicted step 53, the dummy layers of each level are respectively extracted by streaming out.
The extracted dummy layers from each level are then integrated or combined in step 54. Specifically, the integration of the dummy layers of all levels is performed primarily according to the alignment marks.
The integrated dummy layers are then subjected to verification, such as design rule check (DRC) in step 55.
After accomplishing the individual-level check horizontally (step 52) and the integrated TSV/bump check vertically (step 55), the verification of the 3D IC may not even be complete for the reason that the TSV and bump structure of all levels probably connect with each other incorrectly, even when the TSV and bump structure pass the previous checks (such as design rule check and alignment check). In order to prevent and resolve this probable problem, the present embodiment further performs a 3D-IC TSV/bump connection check in step 56. It is appreciated that the TSV and bump structure, or the TSV alone, may be checked in step 56.
In step 561, a connection list file is created to declare the connection of the elements (such as the TSV and bump structure) on the respective levels. In the embodiment, the connection list file adapts a format as illustrated in
Subsequently, in step 562, the 3D-IC port text extracted in step 560 and the connection list file created in step 561 are compared to trace the connection to thereby (e.g., in order to) check connection correctness, for example, by using programming such as Tool Command Language (TCL). According to the result of the comparison performed in step 562, TSV/bump connection errors, if any, may be reported in step 563.
According to the embodiment discussed above, the 3D-IC verification method may be adapted to and integrated with conventional 2D EDA tools, or may be performed alone, for verifying the conformity of 3D ICs with the requirements of function and fabrication. The disclosed embodiment provides a 3D-IC verification method with cost substantially lower than that of a real 3D EDA tool which has not yet even been developed at present.
Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.