Changho Jung

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of pseudo-triple-port SRAM datapaths
- Patent number 12,014,771
- Issue date Jun 18, 2024
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with scan mode
- Patent number 11,763,866
- Issue date Sep 19, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with single-ended sensing using reset-set latch
- Patent number 11,670,351
- Issue date Jun 6, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dual-port SRAM with burst-mode address comparator
- Patent number 11,640,838
- Issue date May 2, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM datapaths
- Patent number 11,615,837
- Issue date Mar 28, 2023
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode operation
- Patent number 11,527,282
- Issue date Dec 13, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst-mode memory with column multiplexer
- Patent number 11,462,263
- Issue date Oct 4, 2022
- QUALCOMM Incorporated
- Changho Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM with robust charge-transfer sense amplification
- Patent number 11,437,091
- Issue date Sep 6, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM
- Patent number 11,398,274
- Issue date Jul 26, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM bitcell architecture
- Patent number 11,361,817
- Issue date Jun 14, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding for pseudo-triple-port SRAM
- Patent number 11,302,388
- Issue date Apr 12, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with advanced burst mode address comparator
- Patent number 11,270,762
- Issue date Mar 8, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing rock bottom leakage in memory
- Patent number 11,170,845
- Issue date Nov 9, 2021
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining a voltage and/or frequency for a performance mode
- Patent number 11,092,646
- Issue date Aug 17, 2021
- QUALCOMM Incorporated
- Sonia Ghosh
- G01 - MEASURING TESTING
Information Patent Grant
SRAM with burst mode operation
- Patent number 10,923,185
- Issue date Feb 16, 2021
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Write driver and pre-charge circuitry for high performance pseudo-d...
- Patent number 10,916,275
- Issue date Feb 9, 2021
- QUALCOMM Incorporated
- Sonia Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode address comparator
- Patent number 10,770,132
- Issue date Sep 8, 2020
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo dual port memory
- Patent number 10,061,542
- Issue date Aug 28, 2018
- QUALCOMM Incorporated
- Tony Chung Yiu Kwok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed level shifter
- Patent number 9,997,208
- Issue date Jun 12, 2018
- QUALCOMM Incorporated
- Chulmin Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sense amplifier enabling scheme
- Patent number 9,978,444
- Issue date May 22, 2018
- QUALCOMM Incorporated
- Tony Chung Yiu Kwok
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for latching data including AND-NOR or OR-NAND...
- Patent number 9,941,881
- Issue date Apr 10, 2018
- QUALCOMM Incorporated
- Changho Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient sense amplifier shifting for memory redundancy
- Patent number 9,905,316
- Issue date Feb 27, 2018
- QUALCOMM Incorporated
- Sonia Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing circuit for memories
- Patent number 9,858,988
- Issue date Jan 2, 2018
- QUALCOMM Incorporated
- Sonia Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Overlapping precharge and data write
- Patent number 9,685,210
- Issue date Jun 20, 2017
- QUALCOMM Incorporated
- Sonia Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage high sigma multi-port memory control
- Patent number 9,653,152
- Issue date May 16, 2017
- QUALCOMM Incorporated
- Tony Chung Yiu Kwok
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell with improved write margin
- Patent number 9,646,681
- Issue date May 9, 2017
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for writing data to memory array circuits
- Patent number 9,536,578
- Issue date Jan 3, 2017
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed pseudo-dual-port memory with separate precharge controls
- Patent number 9,520,165
- Issue date Dec 13, 2016
- QUALCOMM Incorporated
- Nishith Nitin Desai
- G11 - INFORMATION STORAGE
Information Patent Grant
Wide-range level-shifter
- Patent number 9,432,022
- Issue date Aug 30, 2016
- QUALCOMM Incorporated
- Changho Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pseudo dual port memory with dual latch flip-flop
- Patent number 9,324,416
- Issue date Apr 26, 2016
- QUALCOMM Incorporated
- Sei Seung Yoon
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SRAM with Scan Mode
- Publication number 20230307020
- Publication date Sep 28, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20230223075
- Publication date Jul 13, 2023
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Single-Ended Sensing Using Reset-Set Latch
- Publication number 20230170000
- Publication date Jun 1, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR
- Publication number 20230093852
- Publication date Mar 30, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
BURST-MODE MEMORY WITH COLUMN MULTIPLEXER
- Publication number 20220199152
- Publication date Jun 23, 2022
- QUALCOMM Incorporated
- Changho JUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20220093171
- Publication date Mar 24, 2022
- QUALCOMM Incorporated
- Changho JUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DECODING FOR PSEUDO-TRIPLE-PORT SRAM
- Publication number 20220068369
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SRAM WITH ROBUST CHARGE-TRANSFER SENSE AMPLIFICATION
- Publication number 20220068373
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM
- Publication number 20220068371
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE
- Publication number 20220068360
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH ADVANCED BURST MODE ADDRESS COMPARATOR
- Publication number 20220068370
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Changho JUNG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DETERMINING A VOLTAGE AND/OR FREQUENCY FOR A PERFORMANCE MODE
- Publication number 20210255243
- Publication date Aug 19, 2021
- QUALCOMM Incorporated
- Sonia GHOSH
- G01 - MEASURING TESTING
Information Patent Application
SRAM WITH BURST MODE OPERATION
- Publication number 20210134358
- Publication date May 6, 2021
- Qualcomm Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM LOW-POWER WRITE DRIVER
- Publication number 20210098057
- Publication date Apr 1, 2021
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH BURST MODE OPERATION
- Publication number 20200388328
- Publication date Dec 10, 2020
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-POWER MEMORY
- Publication number 20200335151
- Publication date Oct 22, 2020
- QUALCOMM Incorporated
- Chulmin JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT SENSE AMPLIFIER SHIFTING FOR MEMORY REDUNDANCY
- Publication number 20180033495
- Publication date Feb 1, 2018
- QUALCOMM Incorporated
- Sonia GHOSH
- G11 - INFORMATION STORAGE
Information Patent Application
TIMING CIRCUIT FOR MEMORIES
- Publication number 20180012649
- Publication date Jan 11, 2018
- QUALCOMM Incorporated
- Sonia GHOSH
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER ENABLING SCHEME
- Publication number 20170278563
- Publication date Sep 28, 2017
- QUALCOMM Incorporated
- Tony Chung Yiu KWOK
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO DUAL PORT MEMORY
- Publication number 20170075379
- Publication date Mar 16, 2017
- QUALCOMM Incorporated
- Tony Chung Yiu KWOK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-SPEED PSEUDO-DUAL-PORT MEMORY WITH SEPARATE PRECHARGE CONTROLS
- Publication number 20160372167
- Publication date Dec 22, 2016
- QUALCOMM Incorporated
- Nishith Nitin DESAI
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO DUAL PORT MEMORY
- Publication number 20160055903
- Publication date Feb 25, 2016
- QUALCOMM Incorporated
- Sei Seung YOON
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH A SLEEP MODE
- Publication number 20150310901
- Publication date Oct 29, 2015
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
WIDE-RANGE LEVEL-SHIFTER
- Publication number 20150303921
- Publication date Oct 22, 2015
- QUALCOMM Incorporated
- Changho Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA EFFICIENT LAYOUT WITH PARTIAL TRANSISTORS
- Publication number 20150294694
- Publication date Oct 15, 2015
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT MULTIPORT BITCELL
- Publication number 20150221346
- Publication date Aug 6, 2015
- QUALCOMM Incorporated
- Rakesh VATTIKONDA
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)
- Publication number 20150085554
- Publication date Mar 26, 2015
- QUALCOMM Incorporated
- Esin Terzioglu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ACCESS TIME TRACKING IN DUAL-RAIL SYSTEMS
- Publication number 20150067290
- Publication date Mar 5, 2015
- QUALCOMM Incorporated
- Ritu CHABA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIDE RANGE MULTIPORT BITCELL
- Publication number 20150029782
- Publication date Jan 29, 2015
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
PULSE GENERATOR
- Publication number 20140355365
- Publication date Dec 4, 2014
- Changho Jung
- G11 - INFORMATION STORAGE

Changho Jung

Person

Patents Grantslast 30 patents

Method of pseudo-triple-port SRAM datapaths

SRAM with scan mode

Memory with single-ended sensing using reset-set latch

Pseudo-dual-port SRAM with burst-mode address comparator

Pseudo-triple-port SRAM datapaths

SRAM with burst mode operation

Burst-mode memory with column multiplexer

SRAM with robust charge-transfer sense amplification

Pseudo-triple-port SRAM

Pseudo-triple-port SRAM bitcell architecture

Decoding for pseudo-triple-port SRAM

SRAM with advanced burst mode address comparator

Techniques for reducing rock bottom leakage in memory

Determining a voltage and/or frequency for a performance mode

SRAM with burst mode operation

Write driver and pre-charge circuitry for high performance pseudo-d...

SRAM with burst mode address comparator

Pseudo dual port memory

High-speed level shifter

Sense amplifier enabling scheme

Apparatus and method for latching data including AND-NOR or OR-NAND...

Efficient sense amplifier shifting for memory redundancy

Timing circuit for memories

Overlapping precharge and data write

Low voltage high sigma multi-port memory control

Memory cell with improved write margin

Apparatus and method for writing data to memory array circuits

High-speed pseudo-dual-port memory with separate precharge controls

Wide-range level-shifter

Pseudo dual port memory with dual latch flip-flop

Patents Applicationslast 30 patents

SRAM with Scan Mode

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

Memory with Single-Ended Sensing Using Reset-Set Latch

PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR

BURST-MODE MEMORY WITH COLUMN MULTIPLEXER

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

DECODING FOR PSEUDO-TRIPLE-PORT SRAM

SRAM WITH ROBUST CHARGE-TRANSFER SENSE AMPLIFICATION

PSEUDO-TRIPLE-PORT SRAM

PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE

SRAM WITH ADVANCED BURST MODE ADDRESS COMPARATOR

DETERMINING A VOLTAGE AND/OR FREQUENCY FOR A PERFORMANCE MODE

SRAM WITH BURST MODE OPERATION

SRAM LOW-POWER WRITE DRIVER

SRAM WITH BURST MODE OPERATION

LOW-POWER MEMORY

EFFICIENT SENSE AMPLIFIER SHIFTING FOR MEMORY REDUNDANCY

TIMING CIRCUIT FOR MEMORIES

SENSE AMPLIFIER ENABLING SCHEME

PSEUDO DUAL PORT MEMORY

HIGH-SPEED PSEUDO-DUAL-PORT MEMORY WITH SEPARATE PRECHARGE CONTROLS

PSEUDO DUAL PORT MEMORY

MEMORY WITH A SLEEP MODE

WIDE-RANGE LEVEL-SHIFTER

AREA EFFICIENT LAYOUT WITH PARTIAL TRANSISTORS

AREA EFFICIENT MULTIPORT BITCELL

STATIC NAND CELL FOR TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)

MEMORY ACCESS TIME TRACKING IN DUAL-RAIL SYSTEMS

WIDE RANGE MULTIPORT BITCELL

PULSE GENERATOR