Charles Erickson

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Encryption of configuration stream
- Patent number 6,212,639
- Issue date Apr 3, 2001
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration logic to eliminate signal contention during reconfigu...
- Patent number 6,181,158
- Issue date Jan 30, 2001
- Xilinx, Inc.
- Edmond Y. Cheung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and structure for viewing static signal levels on integrated...
- Patent number 6,100,705
- Issue date Aug 8, 2000
- Xilinx, Inc.
- Charles R. Erickson
- G01 - MEASURING TESTING
Information Patent Grant
Partially reconfigurable FPGA and method of operating same
- Patent number 6,057,704
- Issue date May 2, 2000
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,995,988
- Issue date Nov 30, 1999
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Internal drive circuit providing third input pin state
- Patent number 5,990,704
- Issue date Nov 23, 1999
- Xilinx, Inc.
- Charles R. Erickson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input signal interface with independently controllable pull-up and...
- Patent number 5,969,543
- Issue date Oct 19, 1999
- Xilinx, Inc.
- Charles R. Erickson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration stream encryption
- Patent number 5,970,142
- Issue date Oct 19, 1999
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,961,576
- Issue date Oct 5, 1999
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and method for reading blocks of data from selectable poi...
- Patent number 5,923,614
- Issue date Jul 13, 1999
- Xilinx, Inc.
- Charles R. Erickson
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for testing pumped voltage gates in a programmable gate array
- Patent number 5,920,201
- Issue date Jul 6, 1999
- Xilinx, Inc.
- Alok Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Grant
Lookahead structure for fast scan testing
- Patent number 5,909,453
- Issue date Jun 1, 1999
- Xilinx, Inc.
- Steven H. Kelem
- G01 - MEASURING TESTING
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,844,829
- Issue date Dec 1, 1998
- Xilinx, Inc.
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and structure for loading data into several IC devices
- Patent number 5,838,167
- Issue date Nov 17, 1998
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase-locked delay loop for clock correction
- Patent number 5,815,016
- Issue date Sep 29, 1998
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect architecture for field programmable gate array using v...
- Patent number 5,801,546
- Issue date Sep 1, 1998
- Xilinx, Inc.
- Kerry M. Pierce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and method for reading blocks of data from selectable poi...
- Patent number 5,789,938
- Issue date Aug 4, 1998
- Xilinx, Inc.
- Charles R. Erickson
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration logic to eliminate signal contention during reconfigu...
- Patent number 5,770,951
- Issue date Jun 23, 1998
- Xilinx, Inc.
- Edmond Y. Cheung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect architecture for field programmable gate array
- Patent number 5,760,604
- Issue date Jun 2, 1998
- Xilinx, Inc.
- Kerry M. Pierce
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System comprising field programmable gate array and intelligent memory
- Patent number 5,760,607
- Issue date Jun 2, 1998
- Xilinx, Inc.
- Kenneth E. Leeds
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable parallel and bit serial load apparatus
- Patent number 5,742,531
- Issue date Apr 21, 1998
- Philip M. Freidin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for testing pumped voltage gates in a programmable gate array
- Patent number 5,717,340
- Issue date Feb 10, 1998
- Xilink, Inc.
- Alok Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast pipeline frame full detector
- Patent number 5,694,056
- Issue date Dec 2, 1997
- Xilinx, Inc.
- John E. Mahoney
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked delay loop for clock correction
- Patent number 5,646,564
- Issue date Jul 8, 1997
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for loading data into several IC devices
- Patent number 5,640,106
- Issue date Jun 17, 1997
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous dual port RAM
- Patent number 5,631,577
- Issue date May 20, 1997
- Xilinx, Inc.
- Philip M. Freidin
- G11 - INFORMATION STORAGE
Information Patent Grant
Input signal interface with independently controllable pull-up and...
- Patent number 5,600,271
- Issue date Feb 4, 1997
- Xilinx, Inc.
- Charles R. Erickson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error detection structure and method for serial or parallel data st...
- Patent number 5,598,424
- Issue date Jan 28, 1997
- Xilinx, Inc.
- Charles R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration logic to eliminate signal contention during reconfigu...
- Patent number 5,592,105
- Issue date Jan 7, 1997
- Xilinx, Inc.
- Edmond Y. Cheung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect architecture for field programmable gate array using v...
- Patent number 5,581,199
- Issue date Dec 3, 1996
- Xilinx, Inc.
- Kerry M. Pierce
- H03 - BASIC ELECTRONIC CIRCUITRY

Charles Erickson

Person

Patents Grantslast 30 patents

Encryption of configuration stream

Configuration logic to eliminate signal contention during reconfigu...

Method and structure for viewing static signal levels on integrated...

Partially reconfigurable FPGA and method of operating same

Configurable parallel and bit serial load apparatus

Internal drive circuit providing third input pin state

Input signal interface with independently controllable pull-up and...

Configuration stream encryption

Configurable parallel and bit serial load apparatus

Structure and method for reading blocks of data from selectable poi...

Circuit for testing pumped voltage gates in a programmable gate array

Lookahead structure for fast scan testing

Configurable parallel and bit serial load apparatus

Method and structure for loading data into several IC devices

Phase-locked delay loop for clock correction

Interconnect architecture for field programmable gate array using v...

Structure and method for reading blocks of data from selectable poi...

Configuration logic to eliminate signal contention during reconfigu...

Interconnect architecture for field programmable gate array

System comprising field programmable gate array and intelligent memory

Configurable parallel and bit serial load apparatus

Circuit for testing pumped voltage gates in a programmable gate array

Fast pipeline frame full detector

Phase-locked delay loop for clock correction

Method and structure for loading data into several IC devices

Synchronous dual port RAM

Input signal interface with independently controllable pull-up and...

Error detection structure and method for serial or parallel data st...

Configuration logic to eliminate signal contention during reconfigu...

Interconnect architecture for field programmable gate array using v...