Charvaka Duvvury

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for efficient electrostatic discharge testing and...
- Patent number 10,725,098
- Issue date Jul 28, 2020
- ESD IT2 LLC.
- Charvaka Duvvury
- G01 - MEASURING TESTING
Information Patent Grant
ESD protection using diode-isolated gate-grounded nMOS with diode s...
- Patent number 9,269,703
- Issue date Feb 23, 2016
- Texas Instruments Incorporated
- Ponnarith Pok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection using diode-isolated gate-grounded NMOS with diode s...
- Patent number 8,829,618
- Issue date Sep 9, 2014
- Texas Instruments Incorporated
- Ponnarith Pok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection system optimized at board level
- Patent number 8,755,158
- Issue date Jun 17, 2014
- Texas Instruments Incorporated
- Charvaka Duvvury
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
MOS device with substrate potential elevation for ESD protection
- Patent number 8,530,301
- Issue date Sep 10, 2013
- Texas Instruments Incorporated
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In package ESD protections of IC using a thin film polymer
- Patent number 7,872,841
- Issue date Jan 18, 2011
- Texas Instruments Incorporated
- Yves Leduc
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methodology to guard ESD protection circuits against precharge effects
- Patent number 7,864,494
- Issue date Jan 4, 2011
- Texas Instruments Incorporated
- Chih-Ming Hung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
MOS device with substrate potential elevation
- Patent number 7,838,924
- Issue date Nov 23, 2010
- Texas Instruments Incorporated
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methodology to guard ESD protection circuits against precharge effects
- Patent number 7,746,608
- Issue date Jun 29, 2010
- Texas Instruments Incorporated
- Chih-Ming Hung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Local ESD protection for low-capicitance applications
- Patent number 7,667,243
- Issue date Feb 23, 2010
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit to reduce internal ESD stress on device having multiple pow...
- Patent number 7,595,968
- Issue date Sep 29, 2009
- Texas Instruments Incorporated
- Chih-Ming Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor dual guardring arrangement
- Patent number 7,348,643
- Issue date Mar 25, 2008
- Texas Instruments Incorporated
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guardwall structures for ESD protection
- Patent number 7,282,767
- Issue date Oct 16, 2007
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection for RF power amplifier circuits
- Patent number 7,280,330
- Issue date Oct 9, 2007
- Texas Instruments Incorporated
- Ismail H. Oguzman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local ESD protection for low-capacitance applications
- Patent number 7,277,263
- Issue date Oct 2, 2007
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Body-biased pMOS protection against electrostatic discharge
- Patent number 7,256,460
- Issue date Aug 14, 2007
- Texas Instruments Incorporated
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection device including precharge reduc...
- Patent number 7,212,387
- Issue date May 1, 2007
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design implementation to suppress latchup in voltage tolerant circuits
- Patent number 7,167,350
- Issue date Jan 23, 2007
- Texas Instruments Incorporated
- Jorge Salcedo-Suner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guardwall structures for ESD protection
- Patent number 7,145,204
- Issue date Dec 5, 2006
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection of noise decoupling capacitors
- Patent number 6,934,136
- Issue date Aug 23, 2005
- Texas Instrument Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge testers for undistorted human-body-model an...
- Patent number 6,933,741
- Issue date Aug 23, 2005
- Texas Instruments Incorporated
- Charvaka Duvvury
- G01 - MEASURING TESTING
Information Patent Grant
Substrate pump ESD protection for silicon-on-insulator technologies
- Patent number 6,933,567
- Issue date Aug 23, 2005
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Efficient ESD protection with application for low capacitance I/O pads
- Patent number 6,858,902
- Issue date Feb 22, 2005
- Texas Instruments Incorporated
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Geometry-controllable design blocks of MOS transistors for improved...
- Patent number 6,833,568
- Issue date Dec 21, 2004
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Output buffer and I/O protection circuit for CMOS technology
- Patent number 6,826,026
- Issue date Nov 30, 2004
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Drain-extended MOS ESD protection structure
- Patent number 6,804,095
- Issue date Oct 12, 2004
- Texas Instruments Incorporated
- Keith E. Kunz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spreading the power dissipation in MOS transistors for improved ESD...
- Patent number 6,781,204
- Issue date Aug 24, 2004
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method of low voltage SCR protection for high voltage fa...
- Patent number 6,764,892
- Issue date Jul 20, 2004
- Texas Instruments Incorporated
- Keith E. Kunz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimization and linearization of ESD parasitic capacitance in inte...
- Patent number 6,690,066
- Issue date Feb 10, 2004
- Texas Instruments Incorporated
- Heng-Chih Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Efficient design of substrate triggered ESD protection circuits
- Patent number 6,667,865
- Issue date Dec 23, 2003
- Texas Instruments Incorporated
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
System and Method for Efficient Electrostatic Discharge Testing and...
- Publication number 20180100890
- Publication date Apr 12, 2018
- ESD IT2 LLC.
- Charvaka Duvvury
- G01 - MEASURING TESTING
Information Patent Application
ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE S...
- Publication number 20140342515
- Publication date Nov 20, 2014
- Ponnarith POK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD Protection System Optimized at Board Level
- Publication number 20130293992
- Publication date Nov 7, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Charvaka Duvvury
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE S...
- Publication number 20120112286
- Publication date May 10, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Ponnarith Pok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROSTATIC DISCHARGE PROTECTION HAVING MULTIPLY SEGMENTED DIODES...
- Publication number 20110266624
- Publication date Nov 3, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Charvaka DUVVURY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD Protection Integrated at System Level
- Publication number 20110194220
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Charvaka DUVVURY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES...
- Publication number 20110075306
- Publication date Mar 31, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Yves Leduc
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MOS DEVICE WITH SUBSTRATE POTENTIAL ELEVATION FOR ESD PROTECTION
- Publication number 20110063765
- Publication date Mar 17, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS
- Publication number 20100226056
- Publication date Sep 9, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Chih-Ming Hung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
MOS COMPRISING SUBSTRATE POTENTIAL ELEVATING CIRCUITRY FOR ESD PROT...
- Publication number 20090267154
- Publication date Oct 29, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN PACKAGE ESD PROTECTIONS OF IC USING A THIN FILM POLYMER
- Publication number 20080278873
- Publication date Nov 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Yves Leduc
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Local ESD Protection for Low-Capicitance Applications
- Publication number 20070284666
- Publication date Dec 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor dual guardring arrangement
- Publication number 20070278581
- Publication date Dec 6, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Gianluca Boselli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit to reduce internal ESD stress on device having multiple pow...
- Publication number 20070223163
- Publication date Sep 27, 2007
- Chih-Ming Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS
- Publication number 20070103826
- Publication date May 10, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Chih-Ming Hung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
GUARDWALL STRUCTURES FOR ESD PROTECTION
- Publication number 20060231897
- Publication date Oct 19, 2006
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Guardwall structures for ESD protection
- Publication number 20060231895
- Publication date Oct 19, 2006
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Body-biased pMOS protection against electrostatic discharge
- Publication number 20060113600
- Publication date Jun 1, 2006
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrostatic discharge protection device including precharge reduc...
- Publication number 20060061929
- Publication date Mar 23, 2006
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Local ESD protection for low-capacitance applications
- Publication number 20060050453
- Publication date Mar 9, 2006
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD protection for RF power amplifier circuits
- Publication number 20060050452
- Publication date Mar 9, 2006
- Ismail H. Oguzman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electrostatic discharge testers for undistorted human-body-model an...
- Publication number 20050104613
- Publication date May 19, 2005
- Charvaka Duvvury
- G01 - MEASURING TESTING
Information Patent Application
Design implementation to suppress latchup in voltage tolerant circuits
- Publication number 20050104154
- Publication date May 19, 2005
- Jorge Salcedo-Suner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diode-string substrate-pumped electrostatic discharge protection
- Publication number 20040212936
- Publication date Oct 28, 2004
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Geometry-controllable design blocks of MOS transistors for improved...
- Publication number 20040178453
- Publication date Sep 16, 2004
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Drain-extended MOS ESD protection structure
- Publication number 20040027745
- Publication date Feb 12, 2004
- Keith E. Kunz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device and method of low voltage SCR protection for high voltage fa...
- Publication number 20030222273
- Publication date Dec 4, 2003
- Keith E. Kunz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrate pump ESD protection for silicon-on-insulator technologies
- Publication number 20030213995
- Publication date Nov 20, 2003
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ESD protection of noise decoupling capacitors
- Publication number 20030202311
- Publication date Oct 30, 2003
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Output buffer and I/O protection circuit for CMOS technology
- Publication number 20030048588
- Publication date Mar 13, 2003
- Charvaka Duvvury
- H01 - BASIC ELECTRIC ELEMENTS

Charvaka Duvvury

Person

Patents Grantslast 30 patents

System and method for efficient electrostatic discharge testing and...

ESD protection using diode-isolated gate-grounded nMOS with diode s...

ESD protection using diode-isolated gate-grounded NMOS with diode s...

ESD protection system optimized at board level

MOS device with substrate potential elevation for ESD protection

In package ESD protections of IC using a thin film polymer

Methodology to guard ESD protection circuits against precharge effects

MOS device with substrate potential elevation

Methodology to guard ESD protection circuits against precharge effects

Local ESD protection for low-capicitance applications

Circuit to reduce internal ESD stress on device having multiple pow...

Semiconductor dual guardring arrangement

Guardwall structures for ESD protection

ESD protection for RF power amplifier circuits

Local ESD protection for low-capacitance applications

Body-biased pMOS protection against electrostatic discharge

Electrostatic discharge protection device including precharge reduc...

Design implementation to suppress latchup in voltage tolerant circuits

Guardwall structures for ESD protection

ESD protection of noise decoupling capacitors

Electrostatic discharge testers for undistorted human-body-model an...

Substrate pump ESD protection for silicon-on-insulator technologies

Efficient ESD protection with application for low capacitance I/O pads

Geometry-controllable design blocks of MOS transistors for improved...

Output buffer and I/O protection circuit for CMOS technology

Drain-extended MOS ESD protection structure

Spreading the power dissipation in MOS transistors for improved ESD...

Device and method of low voltage SCR protection for high voltage fa...

Minimization and linearization of ESD parasitic capacitance in inte...

Efficient design of substrate triggered ESD protection circuits

Patents Applicationslast 30 patents

System and Method for Efficient Electrostatic Discharge Testing and...

ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE S...

ESD Protection System Optimized at Board Level

ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE S...

ELECTROSTATIC DISCHARGE PROTECTION HAVING MULTIPLY SEGMENTED DIODES...

ESD Protection Integrated at System Level

LOCAL INTEGRATION OF NON-LINEAR SHEET I INTEGRATED CIRCUIT PACKAGES...

MOS DEVICE WITH SUBSTRATE POTENTIAL ELEVATION FOR ESD PROTECTION

METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS

MOS COMPRISING SUBSTRATE POTENTIAL ELEVATING CIRCUITRY FOR ESD PROT...

IN PACKAGE ESD PROTECTIONS OF IC USING A THIN FILM POLYMER

Local ESD Protection for Low-Capicitance Applications

Semiconductor dual guardring arrangement

Circuit to reduce internal ESD stress on device having multiple pow...

METHODOLOGY TO GUARD ESD PROTECTION CIRCUITS AGAINST PRECHARGE EFFECTS

GUARDWALL STRUCTURES FOR ESD PROTECTION

Guardwall structures for ESD protection

Body-biased pMOS protection against electrostatic discharge

Electrostatic discharge protection device including precharge reduc...

Local ESD protection for low-capacitance applications

ESD protection for RF power amplifier circuits

Electrostatic discharge testers for undistorted human-body-model an...

Design implementation to suppress latchup in voltage tolerant circuits

Diode-string substrate-pumped electrostatic discharge protection

Geometry-controllable design blocks of MOS transistors for improved...

Drain-extended MOS ESD protection structure

Device and method of low voltage SCR protection for high voltage fa...

Substrate pump ESD protection for silicon-on-insulator technologies

ESD protection of noise decoupling capacitors

Output buffer and I/O protection circuit for CMOS technology