Cher Liang Cha

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Method to fabricate horizontal air columns underneath metal inductor
- Patent number 7,573,081
- Issue date Aug 11, 2009
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a cross network of air gaps within IMD layer
- Patent number 7,112,866
- Issue date Sep 26, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to fabricate horizontal air columns underneath metal inductor
- Patent number 7,105,420
- Issue date Sep 12, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a high K metallic dielectric layer
- Patent number 6,764,914
- Issue date Jul 20, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form a cross network of air gaps within IMD layer
- Patent number 6,730,571
- Issue date May 4, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Effective isolation with high aspect ratio shallow trench isolation...
- Patent number 6,680,239
- Issue date Jan 20, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming dual gate oxide thickness on vertical transistors by ion im...
- Patent number 6,610,575
- Issue date Aug 26, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating CMOS device with dual gate electrode
- Patent number 6,605,501
- Issue date Aug 12, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chew-Hoe Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form shallow junction transistors while eliminating short...
- Patent number 6,566,209
- Issue date May 20, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow junction transistors which eliminating shorts due to juncti...
- Patent number 6,531,750
- Issue date Mar 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a small dimensional gate with elevated sourc...
- Patent number 6,518,133
- Issue date Feb 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash device having a large planar area ono interpoly dielectric
- Patent number 6,501,122
- Issue date Dec 31, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming of high K metallic dielectric layer
- Patent number 6,492,242
- Issue date Dec 10, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned elevated transistor
- Patent number 6,483,148
- Issue date Nov 19, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form high performance copper damascene interconnects by d...
- Patent number 6,380,084
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Inc.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned elevated transistor
- Patent number 6,326,272
- Issue date Dec 4, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating CMOS devices featuring dual gate structures a...
- Patent number 6,303,418
- Issue date Oct 16, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form shallow junction transistors while eliminating short...
- Patent number 6,297,109
- Issue date Oct 2, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded polysilicon gate MOSFET
- Patent number 6,252,277
- Issue date Jun 26, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to trap air at the silicon substrate for improving the quali...
- Patent number 6,221,727
- Issue date Apr 24, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form narrow and wide shallow trench isolations with diffe...
- Patent number 6,207,534
- Issue date Mar 27, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of low k dielectric
- Patent number 6,150,232
- Issue date Nov 21, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making spiral-type RF inductors having a high quality fac...
- Patent number 6,140,197
- Issue date Oct 31, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Shau-Fu Sanford Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Production of reversed flash memory device
- Patent number 6,096,604
- Issue date Aug 1, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Cher Liang Cha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus to image metallic patches embedded in a non-me...
- Patent number 6,064,201
- Issue date May 16, 2000
- Chartered Semiconductor Manufacturing Ltd.
- Cher Liang Randall Cha
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method to fabricate a large planar area ONO interpoly dielectric in...
- Patent number 6,051,467
- Issue date Apr 18, 2000
- Chartered Semiconductor Manufacturing, Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method to fabricate horizontal air columns underneath metal inductor
- Publication number 20070007623
- Publication date Jan 11, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form a cross network of air gaps within IMD layer
- Publication number 20040175896
- Publication date Sep 9, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thermal circuitry
- Publication number 20030107114
- Publication date Jun 12, 2003
- Yee Loy Lam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a high K metallic dielectric layer
- Publication number 20030104673
- Publication date Jun 5, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Alex See
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned elevated transistor
- Publication number 20020090787
- Publication date Jul 11, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form shallow junction transistors while eliminating short...
- Publication number 20020011629
- Publication date Jan 31, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form shallow junction transistors while eliminating short...
- Publication number 20020003264
- Publication date Jan 10, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Lap Chan
- H01 - BASIC ELECTRIC ELEMENTS

Cher Liang Cha

Person

Patents Grantslast 30 patents

Method to fabricate horizontal air columns underneath metal inductor

Method to form a cross network of air gaps within IMD layer

Method to fabricate horizontal air columns underneath metal inductor

Method of forming a high K metallic dielectric layer

Method to form a cross network of air gaps within IMD layer

Effective isolation with high aspect ratio shallow trench isolation...

Forming dual gate oxide thickness on vertical transistors by ion im...

Method of fabricating CMOS device with dual gate electrode

Method to form shallow junction transistors while eliminating short...

Shallow junction transistors which eliminating shorts due to juncti...

Method for fabricating a small dimensional gate with elevated sourc...

Flash device having a large planar area ono interpoly dielectric

Method of forming of high K metallic dielectric layer

Self-aligned elevated transistor

Method to form high performance copper damascene interconnects by d...

Method for forming self-aligned elevated transistor

Method of fabricating CMOS devices featuring dual gate structures a...

Method to form shallow junction transistors while eliminating short...

Embedded polysilicon gate MOSFET

Method to trap air at the silicon substrate for improving the quali...

Method to form narrow and wide shallow trench isolations with diffe...

Formation of low k dielectric

Method of making spiral-type RF inductors having a high quality fac...

Production of reversed flash memory device

Method and apparatus to image metallic patches embedded in a non-me...

Method to fabricate a large planar area ONO interpoly dielectric in...

Patents Applicationslast 30 patents

Method to fabricate horizontal air columns underneath metal inductor

Method to form a cross network of air gaps within IMD layer

Thermal circuitry

Method of forming a high K metallic dielectric layer

Self-aligned elevated transistor

Method to form shallow junction transistors while eliminating short...

Method to form shallow junction transistors while eliminating short...