Chin L. Chen

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient modular reduction and modular multiplication
- Patent number 7,627,114
- Issue date Dec 1, 2009
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost symbol error correction coding and decoding
- Patent number 7,487,425
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
(18, 9) Error correction code for double error correction and tripl...
- Patent number 7,243,293
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for encoding special uncorrectable errors in a...
- Patent number 7,171,591
- Issue date Jan 30, 2007
- International Business Machines Corporation
- Chin-Long Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Symbol level error correction codes which protect against memory ch...
- Patent number 7,093,183
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hardware implementation for modular multiplication using a pluralit...
- Patent number 7,080,110
- Issue date Jul 18, 2006
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cycle symbol level error correction and memory system
- Patent number 7,028,248
- Issue date Apr 11, 2006
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for calculating modular multiplicative inverse
- Patent number 6,978,016
- Issue date Dec 20, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for modular exponentiation
- Patent number 6,963,977
- Issue date Nov 8, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for implementing the chinese remainder theorem
- Patent number 6,963,645
- Issue date Nov 8, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block-serial finite field multipliers
- Patent number 6,957,243
- Issue date Oct 18, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for checking modular multiplication
- Patent number 6,914,983
- Issue date Jul 5, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelining operations in a system for performing modular multiplica...
- Patent number 6,804,696
- Issue date Oct 12, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware implementation for modular multiplication using a pluralit...
- Patent number 6,763,365
- Issue date Jul 13, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
(146,130) error correction code utilizing address information
- Patent number 6,751,769
- Issue date Jun 15, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction coding of data blocks with included parity bits
- Patent number 6,675,349
- Issue date Jan 6, 2004
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Extended error correction for SEC-DED codes with package error dete...
- Patent number 6,675,341
- Issue date Jan 6, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual functioning symbol error correction code
- Patent number 6,539,513
- Issue date Mar 25, 2003
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating special uncorrectable error codes for failure isolation
- Patent number 6,519,736
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single symbol correction double symbol detection code employing a m...
- Patent number 6,463,563
- Issue date Oct 8, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method system and program products for error correction code conver...
- Patent number 6,460,157
- Issue date Oct 1, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting address faults in an ECC-protected memory
- Patent number 6,457,154
- Issue date Sep 24, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
String search apparatus and method for data compression
- Patent number 6,392,571
- Issue date May 21, 2002
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory card identification system
- Patent number 6,386,456
- Issue date May 14, 2002
- International Business Machines Corporation
- Chin-Long Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for writing single width bar codes on semiconductors wafers
- Patent number 6,179,207
- Issue date Jan 30, 2001
- International Business Machines Corporation
- Douglas Craig Bossen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error propagation operating mode for error correcting code retrofit...
- Patent number 6,044,483
- Issue date Mar 28, 2000
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting code retrofit method and apparatus for multiple me...
- Patent number 6,018,817
- Issue date Jan 25, 2000
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting code retrofit method and apparatus for multiple me...
- Patent number 6,009,548
- Issue date Dec 28, 1999
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual error correction code
- Patent number 5,956,351
- Issue date Sep 21, 1999
- International Business Machines Corporation
- Douglas Craig Bossen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fault tolerant system based on voting
- Patent number 5,907,671
- Issue date May 25, 1999
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for encoding special uncorrectable errors in a...
- Publication number 20050188292
- Publication date Aug 25, 2005
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS FOR CALCULATING MODULAR MULTIPLICATIVE INVERSE
- Publication number 20050185791
- Publication date Aug 25, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS AND METHODS FOR MODULAR EXPONENTIATION
- Publication number 20050188209
- Publication date Aug 25, 2005
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
(18, 9) Error correction code for double error correction and tripl...
- Publication number 20050149834
- Publication date Jul 7, 2005
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hardware implementation for modular multiplication using a pluralit...
- Publication number 20040210614
- Publication date Oct 21, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular reduction method which recognizes special conditions
- Publication number 20040120516
- Publication date Jun 24, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient modular reduction and modular multiplication
- Publication number 20040066934
- Publication date Apr 8, 2004
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Check sum generation for modular reduction
- Publication number 20040039767
- Publication date Feb 26, 2004
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
(146,130) error correction code utilizing address information
- Publication number 20030140300
- Publication date Jul 24, 2003
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Block-serial finite field multipliers
- Publication number 20030093450
- Publication date May 15, 2003
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symbol level error correction codes which protect against memory ch...
- Publication number 20020188909
- Publication date Dec 12, 2002
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-cycle symbol level error correction and memory system
- Publication number 20020152444
- Publication date Oct 17, 2002
- International Business Machines Corporation
- Chin-Long Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hardware implementation for modular multiplication using a pluralit...
- Publication number 20020120658
- Publication date Aug 29, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for modular multiplication
- Publication number 20020116429
- Publication date Aug 22, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelining operations in a system for performing modular multiplica...
- Publication number 20020116430
- Publication date Aug 22, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for checking modular multiplication
- Publication number 20020110240
- Publication date Aug 15, 2002
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for implementing the chinese remainder theorem
- Publication number 20020110241
- Publication date Aug 15, 2002
- International Business Machines Corporation
- Chin-Long Chen
- G06 - COMPUTING CALCULATING COUNTING

Chin L. Chen

Person

Patents Grantslast 30 patents

Efficient modular reduction and modular multiplication

Low cost symbol error correction coding and decoding

(18, 9) Error correction code for double error correction and tripl...

Method and apparatus for encoding special uncorrectable errors in a...

Symbol level error correction codes which protect against memory ch...

Hardware implementation for modular multiplication using a pluralit...

Multi-cycle symbol level error correction and memory system

Circuits for calculating modular multiplicative inverse

Circuits and methods for modular exponentiation

Method for implementing the chinese remainder theorem

Block-serial finite field multipliers

Method for checking modular multiplication

Pipelining operations in a system for performing modular multiplica...

Hardware implementation for modular multiplication using a pluralit...

(146,130) error correction code utilizing address information

Error correction coding of data blocks with included parity bits

Extended error correction for SEC-DED codes with package error dete...

Dual functioning symbol error correction code

Generating special uncorrectable error codes for failure isolation

Single symbol correction double symbol detection code employing a m...

Method system and program products for error correction code conver...

Detecting address faults in an ECC-protected memory

String search apparatus and method for data compression

Memory card identification system

Method for writing single width bar codes on semiconductors wafers

Error propagation operating mode for error correcting code retrofit...

Error correcting code retrofit method and apparatus for multiple me...

Error correcting code retrofit method and apparatus for multiple me...

Dual error correction code

Fault tolerant system based on voting

Patents Applicationslast 30 patents

Method and apparatus for encoding special uncorrectable errors in a...

CIRCUITS FOR CALCULATING MODULAR MULTIPLICATIVE INVERSE

CIRCUITS AND METHODS FOR MODULAR EXPONENTIATION

(18, 9) Error correction code for double error correction and tripl...

Hardware implementation for modular multiplication using a pluralit...

Modular reduction method which recognizes special conditions

Efficient modular reduction and modular multiplication

Check sum generation for modular reduction

(146,130) error correction code utilizing address information

Block-serial finite field multipliers

Symbol level error correction codes which protect against memory ch...

Multi-cycle symbol level error correction and memory system

Hardware implementation for modular multiplication using a pluralit...

System and method for modular multiplication

Pipelining operations in a system for performing modular multiplica...

Method for checking modular multiplication

Method for implementing the chinese remainder theorem