Chiu-Ming Chou

Person

Kao-Hsiung, TW

People

Patents Grantslast 30 patents

Information Patent Grant
3D chip package based on vertical-through-via connector
- Patent number 12,176,278
- Issue date Dec 24, 2024
- iCometrue Company Ltd.
- Ping-Jung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and method for fabricating the same
- Patent number 8,836,146
- Issue date Sep 16, 2014
- QUALCOMM Incorporated
- Chien-Kang Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level processing method and structure to manufacture two kind...
- Patent number 8,674,507
- Issue date Mar 18, 2014
- Megit Acquisition Corp.
- Chien-Kang Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit (IC) chip and method for fabricating the same
- Patent number 8,592,977
- Issue date Nov 26, 2013
- Megit Acquisition Corp.
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure of gold bumps and gold conductors on one IC die and metho...
- Patent number 8,581,404
- Issue date Nov 12, 2013
- Megit Acquistion Corp.
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very thick metal interconnection scheme in IC chips
- Patent number 8,552,559
- Issue date Oct 8, 2013
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip structure
- Patent number 8,519,552
- Issue date Aug 27, 2013
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked chip package with redistribution lines
- Patent number 8,426,958
- Issue date Apr 23, 2013
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal pad or metal bump over pad exposed by passivation layer
- Patent number 8,399,989
- Issue date Mar 19, 2013
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with coil element over passivation layer
- Patent number 8,362,588
- Issue date Jan 29, 2013
- Megica Corporation
- Wen-Chieh Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonding method for preventing polymer cracking
- Patent number 8,344,524
- Issue date Jan 1, 2013
- Megica Corporation
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with post-passivation scheme formed over passiva...
- Patent number 8,319,354
- Issue date Nov 27, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with a bonding pad having contact and test areas
- Patent number 8,304,766
- Issue date Nov 6, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top layers of metal for integrated circuits
- Patent number 8,304,907
- Issue date Nov 6, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with passivation layer comprising metal intercon...
- Patent number 8,242,601
- Issue date Aug 14, 2012
- Megica Corporation
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Connection between a semiconductor chip and a circuit component wit...
- Patent number 8,198,729
- Issue date Jun 12, 2012
- Megica Corporation
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip and method for fabricating the same
- Patent number 8,168,527
- Issue date May 1, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip structure
- Patent number 8,159,074
- Issue date Apr 17, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pad on IC substrate and method for making the same
- Patent number 8,148,822
- Issue date Apr 3, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post passivation interconnection process and structures
- Patent number 8,120,181
- Issue date Feb 21, 2012
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip structure
- Patent number 8,022,544
- Issue date Sep 20, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post passivation interconnection process and structures
- Patent number 8,018,060
- Issue date Sep 13, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post passivation interconnection schemes on top of the IC chips
- Patent number 8,013,449
- Issue date Sep 6, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post passivation interconnection structures
- Patent number 8,008,775
- Issue date Aug 30, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with post-passivation scheme formed over passiva...
- Patent number 8,004,092
- Issue date Aug 23, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with coil element over passivation layer
- Patent number 7,985,653
- Issue date Jul 26, 2011
- Megica Corporation
- Wen-Chieh Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip structure with bumps and testing pads
- Patent number 7,977,803
- Issue date Jul 12, 2011
- Megica Corporation
- Nick Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked chip package with redistribution lines
- Patent number 7,973,401
- Issue date Jul 5, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip structure
- Patent number 7,964,973
- Issue date Jun 21, 2011
- Megica Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a double embossing structure
- Patent number 7,960,269
- Issue date Jun 14, 2011
- Megica Corporation
- Hsin-Jung Lo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR
- Publication number 20250125241
- Publication date Apr 17, 2025
- iCometrue Company Ltd.
- Ping-Jung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR
- Publication number 20220384326
- Publication date Dec 1, 2022
- iCometrue Company Ltd.
- Ping-Jung Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STRUCTURE
- Publication number 20110291272
- Publication date Dec 1, 2011
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVA...
- Publication number 20110266669
- Publication date Nov 3, 2011
- MEGICA CORPORATION
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES
- Publication number 20110241183
- Publication date Oct 6, 2011
- MEGICA Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER
- Publication number 20110233776
- Publication date Sep 29, 2011
- MEGICA Corporation
- Wen-Chieh Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE
- Publication number 20110215469
- Publication date Sep 8, 2011
- MEGICA Corporation
- HSIN-JUNG LO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME
- Publication number 20110204510
- Publication date Aug 25, 2011
- MEGICA Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP
- Publication number 20110198589
- Publication date Aug 18, 2011
- MEGICA Corporation
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STRUCTURE WITH BUMPS AND TESTING PADS
- Publication number 20110049515
- Publication date Mar 3, 2011
- MEGICA Corporation
- Nick Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME
- Publication number 20090291554
- Publication date Nov 26, 2009
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Chip with Passivation Layer Comprising Metal Intercon...
- Publication number 20090218687
- Publication date Sep 3, 2009
- MEGICA CORPORATION
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
- Publication number 20090146305
- Publication date Jun 11, 2009
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME
- Publication number 20090108453
- Publication date Apr 30, 2009
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Over-passivation process of forming polymer layer over IC chip
- Publication number 20090111261
- Publication date Apr 30, 2009
- MEGICA CORPORATION
- Ying-Chih Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor chip with coil element over passivation layer
- Publication number 20090104769
- Publication date Apr 23, 2009
- MEGICA CORPORATION
- Wen-Chieh Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Chip Package With Redistribution Lines
- Publication number 20090057900
- Publication date Mar 5, 2009
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure of Gold Bumps and Gold Conductors on one IC Die and Metho...
- Publication number 20090057894
- Publication date Mar 5, 2009
- MEGICA CORPORATION
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reliable metal bumps on top of I/O pads after removal of test probe...
- Publication number 20080290520
- Publication date Nov 27, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVA...
- Publication number 20080265413
- Publication date Oct 30, 2008
- MEGICA CORPORATION
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS
- Publication number 20080251925
- Publication date Oct 16, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Post Passivation Interconnection Schemes On Top Of The IC Chips
- Publication number 20080251924
- Publication date Oct 16, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip structure with bumps and testing pads
- Publication number 20080224326
- Publication date Sep 18, 2008
- MEGICA CORPORATION
- Nick Kuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP STRUCTURE AND METHOD FOR FABRICATION THE SAME
- Publication number 20080146018
- Publication date Jun 19, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Post Passivation Interconnection Process And Structures
- Publication number 20080128910
- Publication date Jun 5, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Top layers of metal for integrated circuits
- Publication number 20080121943
- Publication date May 29, 2008
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME
- Publication number 20080054457
- Publication date Mar 6, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS
- Publication number 20080042297
- Publication date Feb 21, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Top Layers of Metal for Integrated Circuits
- Publication number 20080045007
- Publication date Feb 21, 2008
- MEGICA CORPORATION
- Mou-Shiung Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit (IC) chip and method for fabricating the same
- Publication number 20080001290
- Publication date Jan 3, 2008
- MEGICA CORPORATION
- Chiu-Ming Chou
- H01 - BASIC ELECTRIC ELEMENTS

Chiu-Ming Chou

Person

Patents Grantslast 30 patents

3D chip package based on vertical-through-via connector

Chip package and method for fabricating the same

Wafer level processing method and structure to manufacture two kind...

Integrated circuit (IC) chip and method for fabricating the same

Structure of gold bumps and gold conductors on one IC die and metho...

Very thick metal interconnection scheme in IC chips

Chip structure

Stacked chip package with redistribution lines

Metal pad or metal bump over pad exposed by passivation layer

Semiconductor chip with coil element over passivation layer

Wire bonding method for preventing polymer cracking

Semiconductor chip with post-passivation scheme formed over passiva...

Semiconductor chip with a bonding pad having contact and test areas

Top layers of metal for integrated circuits

Semiconductor chip with passivation layer comprising metal intercon...

Connection between a semiconductor chip and a circuit component wit...

Semiconductor chip and method for fabricating the same

Chip structure

Bonding pad on IC substrate and method for making the same

Post passivation interconnection process and structures

Chip structure

Post passivation interconnection process and structures

Post passivation interconnection schemes on top of the IC chips

Post passivation interconnection structures

Semiconductor chip with post-passivation scheme formed over passiva...

Semiconductor chip with coil element over passivation layer

Chip structure with bumps and testing pads

Stacked chip package with redistribution lines

Chip structure

Method for forming a double embossing structure

Patents Applicationslast 30 patents

3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR

3D CHIP PACKAGE BASED ON VERTICAL-THROUGH-VIA CONNECTOR

CHIP STRUCTURE

SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVA...

STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES

SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER

METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE

CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR CHIP

CHIP STRUCTURE WITH BUMPS AND TESTING PADS

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

Semiconductor Chip with Passivation Layer Comprising Metal Intercon...

POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME

Over-passivation process of forming polymer layer over IC chip

Semiconductor chip with coil element over passivation layer

Stacked Chip Package With Redistribution Lines

Structure of Gold Bumps and Gold Conductors on one IC Die and Metho...

Reliable metal bumps on top of I/O pads after removal of test probe...

SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVA...

TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS

Post Passivation Interconnection Schemes On Top Of The IC Chips

Chip structure with bumps and testing pads

CHIP STRUCTURE AND METHOD FOR FABRICATION THE SAME

Post Passivation Interconnection Process And Structures

Top layers of metal for integrated circuits

SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME

POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS

Top Layers of Metal for Integrated Circuits

Integrated circuit (IC) chip and method for fabricating the same