Christian Georg Geissler

Person

Teugn, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Radiation source device
- Patent number 12,158,448
- Issue date Dec 3, 2024
- Infineon Technologies AG
- Derek Debie
- G01 - MEASURING TESTING
Information Patent Grant
Radio-frequency devices and methods for producing radio-frequency d...
- Patent number 12,040,543
- Issue date Jul 16, 2024
- Infineon Technologies AG
- Walter Hartner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,955,462
- Issue date Apr 9, 2024
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of stress decoupling and particle filter on a single wa...
- Patent number 11,505,450
- Issue date Nov 22, 2022
- Infineon Technologies AG
- Florian Brandl
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Wafer level package structure with internal conductive layer
- Patent number 11,424,209
- Issue date Aug 23, 2022
- Intel Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package stacking using chip to wafer bonding
- Patent number 11,239,199
- Issue date Feb 1, 2022
- Intel Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having cutouts in an encapsulation material a...
- Patent number 11,145,563
- Issue date Oct 12, 2021
- Infineon Technologies AG
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device including redistribution layer pad having a void
- Patent number 10,916,484
- Issue date Feb 9, 2021
- Infineon Technologies AG
- Robert Fehler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of stress decoupling and particle filter on a single wa...
- Patent number 10,899,604
- Issue date Jan 26, 2021
- Infineon Technologies AG
- Florian Brandl
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor die package with more than one hanging die
- Patent number 10,854,590
- Issue date Dec 1, 2020
- Intel IP Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,816,742
- Issue date Oct 27, 2020
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Method for producing packaged MEMS assemblies at the wafer level, a...
- Patent number 10,793,429
- Issue date Oct 6, 2020
- Infineon Technologies AG
- Matthias Steiert
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Electronic components having three-dimensional capacitors in a meta...
- Patent number 10,741,486
- Issue date Aug 11, 2020
- Intel Corporation
- Klaus Reingruber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package structure with internal conductive layer
- Patent number 10,672,731
- Issue date Jun 2, 2020
- Intel IP Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer with conductive routing exposed on sidewalls
- Patent number 10,651,102
- Issue date May 12, 2020
- Intel IP Corporation
- Klaus Reingruber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing packaged MEMS assemblies at the wafer level, a...
- Patent number 10,584,028
- Issue date Mar 10, 2020
- Infineon Technologies AG
- Matthias Steiert
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor package with a through port for sensor applications
- Patent number 10,549,985
- Issue date Feb 4, 2020
- Infineon Technologies AG
- Dominic Maier
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Semiconductor package having a variable redistribution layer thickness
- Patent number 10,553,538
- Issue date Feb 4, 2020
- Intel Corporation
- Klaus Jürgen Reingruber
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Microelectronic package having a passive microelectronic device dis...
- Patent number 10,522,454
- Issue date Dec 31, 2019
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical device and a method for forming an electrical device
- Patent number 10,522,485
- Issue date Dec 31, 2019
- Intel IP Corporation
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical wire connections for integrated circuit package
- Patent number 10,490,527
- Issue date Nov 26, 2019
- Intel IP Corporation
- Christian Geissler
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Advanced node cost reduction by ESD interposer
- Patent number 10,446,541
- Issue date Oct 15, 2019
- Intel IP Corporation
- Georg Seidemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package with illuminated backside exterior
- Patent number 10,411,000
- Issue date Sep 10, 2019
- Intel IP Corporation
- Marc Stephan Dittes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System-in-package devices and methods for forming system-in-package...
- Patent number 10,403,609
- Issue date Sep 3, 2019
- Intel IP Corporation
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package configurations to reduce stiffness
- Patent number 10,373,844
- Issue date Aug 6, 2019
- Intel IP Corporation
- Sven Albers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low thermal resistance hanging die package
- Patent number 10,347,558
- Issue date Jul 9, 2019
- Intel IP Corporation
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectromechanical system (MEMS) on application specific integr...
- Patent number 10,301,176
- Issue date May 28, 2019
- Intel IP Corporation
- Gerald Ofner
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Flexible band wearable electronic device
- Patent number 10,228,725
- Issue date Mar 12, 2019
- Intel IP Corporation
- Sven Albers
- A44 - HABERDASHERY JEWELLERY
Information Patent Grant
Integrated circuit packages including an optical redistribution layer
- Patent number 10,209,466
- Issue date Feb 19, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Grant
Integrated circuit package
- Patent number 10,157,869
- Issue date Dec 18, 2018
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSFORMER ARRANGEMENT
- Publication number 20240312975
- Publication date Sep 19, 2024
- Infineon Technologies Austria AG
- Horst Theuss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20240213225
- Publication date Jun 27, 2024
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN-OUT WAFER-LEVEL PACKAGES AND ASSOCIATED PRODUCTION METHODS
- Publication number 20240196757
- Publication date Jun 13, 2024
- INFINEON TECHNOLOGIES AG
- Horst THEUSS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RADIATION SOURCE DEVICE
- Publication number 20230194478
- Publication date Jun 22, 2023
- INFINEON TECHNOLOGIES AG
- Derek Debie
- G01 - MEASURING TESTING
Information Patent Application
RADIO-FREQUENCY DEVICES AND METHODS FOR PRODUCING RADIO-FREQUENCY D...
- Publication number 20220247089
- Publication date Aug 4, 2022
- INFINEON TECHNOLOGIES AG
- Walter HARTNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20220108976
- Publication date Apr 7, 2022
- Intel Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION OF STRESS DECOUPLING AND PARTICLE FILTER ON A SINGLE WA...
- Publication number 20210032097
- Publication date Feb 4, 2021
- INFINEON TECHNOLOGIES AG
- Florian BRANDL
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
INTEGRATION OF STRESS DECOUPLING AND PARTICLE FILTER ON A SINGLE WA...
- Publication number 20200331748
- Publication date Oct 22, 2020
- INFINEON TECHNOLOGIES AG
- Florian BRANDL
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER
- Publication number 20200273832
- Publication date Aug 27, 2020
- Intel IP Corporation
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE
- Publication number 20200176436
- Publication date Jun 4, 2020
- Intel IP Corporation
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING PACKAGED MEMS ASSEMBLIES AT THE WAFER LEVEL, A...
- Publication number 20200156933
- Publication date May 21, 2020
- INFINEON TECHNOLOGIES AG
- Matthias Steiert
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICES HAVING CUTOUTS IN AN ENCAPSULATION MATERIAL A...
- Publication number 20200006174
- Publication date Jan 2, 2020
- INFINEON TECHNOLOGIES AG
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPLB/EWLB BASED POP FOR HBM OR CUSTOMIZED PACKAGE STACK
- Publication number 20190206833
- Publication date Jul 4, 2019
- Intel IP Corporation
- Thorsten MEYER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR APPARATUSES WITH RADIO-FREQUENCY LINE ELEMENTS, AND A...
- Publication number 20190198455
- Publication date Jun 27, 2019
- INFINEON TECHNOLOGIES AG
- Walter HARTNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL FIBER CONNECTION ON PACKAGE EDGE
- Publication number 20190121041
- Publication date Apr 25, 2019
- Intel IP Corporation
- Sven Albers
- G02 - OPTICS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER
- Publication number 20190072732
- Publication date Mar 7, 2019
- Intel IP Corporation
- Georg Seidemann
- G02 - OPTICS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS
- Publication number 20190043800
- Publication date Feb 7, 2019
- Intel IP Corporation
- Klaus Jürgen REINGRUBER
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE
- Publication number 20180374819
- Publication date Dec 27, 2018
- Christian Geissler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE INCLUDING REDISTRIBUTION LAYER PAD HAVING A VOID
- Publication number 20180374769
- Publication date Dec 27, 2018
- INFINEON TECHNOLOGIES AG
- Robert Fehler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER
- Publication number 20180358317
- Publication date Dec 13, 2018
- Sven ALBERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS
- Publication number 20180342431
- Publication date Nov 29, 2018
- Intel IP Corporation
- Klaus Reingruber
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
System-in-Package Devices and Methods for Forming System-in-Package...
- Publication number 20180331080
- Publication date Nov 15, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical device and a method for forming an electrical device
- Publication number 20180331053
- Publication date Nov 15, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STACKING USING CHIP TO WAFER BONDING
- Publication number 20180331070
- Publication date Nov 15, 2018
- Intel IP Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING PACKAGED MEMS ASSEMBLIES AT THE WAFER LEVEL, A...
- Publication number 20180327258
- Publication date Nov 15, 2018
- INFINEON TECHNOLOGIES AG
- Matthias Steiert
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DIS...
- Publication number 20180286799
- Publication date Oct 4, 2018
- Intel Corporation
- Thorsten Meyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROBUST INTERMETALLIC COMPOUND LAYER INTERFACE FOR PACKAGE IN PACKAG...
- Publication number 20180226377
- Publication date Aug 9, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW THERMAL RESISTANCE HANGING DIE PACKAGE
- Publication number 20180218962
- Publication date Aug 2, 2018
- Intel IP Corporation
- Christian GEISSLER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED NODE COST REDUCTION BY ESD INTERPOSER
- Publication number 20180204831
- Publication date Jul 19, 2018
- Intel IP Corporation
- Georg SEIDEMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTROMECHANICAL SYSTEM (MEMS) ON APPLICATION SPECIFIC INTEGR...
- Publication number 20180186627
- Publication date Jul 5, 2018
- Intel IP Corporation
- Gerald Ofner
- B81 - MICRO-STRUCTURAL TECHNOLOGY

Christian Georg Geissler

Person

Patents Grantslast 30 patents

Radiation source device

Radio-frequency devices and methods for producing radio-frequency d...

Package stacking using chip to wafer bonding

Integration of stress decoupling and particle filter on a single wa...

Wafer level package structure with internal conductive layer

Package stacking using chip to wafer bonding

Semiconductor devices having cutouts in an encapsulation material a...

Electronic device including redistribution layer pad having a void

Integration of stress decoupling and particle filter on a single wa...

Semiconductor die package with more than one hanging die

Integrated circuit packages including an optical redistribution layer

Method for producing packaged MEMS assemblies at the wafer level, a...

Electronic components having three-dimensional capacitors in a meta...

Wafer level package structure with internal conductive layer

Interposer with conductive routing exposed on sidewalls

Method for producing packaged MEMS assemblies at the wafer level, a...

Semiconductor package with a through port for sensor applications

Semiconductor package having a variable redistribution layer thickness

Microelectronic package having a passive microelectronic device dis...

Electrical device and a method for forming an electrical device

Vertical wire connections for integrated circuit package

Advanced node cost reduction by ESD interposer

Microelectronic package with illuminated backside exterior

System-in-package devices and methods for forming system-in-package...

Integrated circuit package configurations to reduce stiffness

Low thermal resistance hanging die package

Microelectromechanical system (MEMS) on application specific integr...

Flexible band wearable electronic device

Integrated circuit packages including an optical redistribution layer

Integrated circuit package

Patents Applicationslast 30 patents

TRANSFORMER ARRANGEMENT

PACKAGE STACKING USING CHIP TO WAFER BONDING

FAN-OUT WAFER-LEVEL PACKAGES AND ASSOCIATED PRODUCTION METHODS

RADIATION SOURCE DEVICE

RADIO-FREQUENCY DEVICES AND METHODS FOR PRODUCING RADIO-FREQUENCY D...

PACKAGE STACKING USING CHIP TO WAFER BONDING

INTEGRATION OF STRESS DECOUPLING AND PARTICLE FILTER ON A SINGLE WA...

INTEGRATION OF STRESS DECOUPLING AND PARTICLE FILTER ON A SINGLE WA...

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

SEMICONDUCTOR DIE PACKAGE WITH MORE THAN ONE HANGING DIE

METHOD FOR PRODUCING PACKAGED MEMS ASSEMBLIES AT THE WAFER LEVEL, A...

SEMICONDUCTOR DEVICES HAVING CUTOUTS IN AN ENCAPSULATION MATERIAL A...

EPLB/EWLB BASED POP FOR HBM OR CUSTOMIZED PACKAGE STACK

SEMICONDUCTOR APPARATUSES WITH RADIO-FREQUENCY LINE ELEMENTS, AND A...

OPTICAL FIBER CONNECTION ON PACKAGE EDGE

INTEGRATED CIRCUIT PACKAGES INCLUDING AN OPTICAL REDISTRIBUTION LAYER

SEMICONDUCTOR PACKAGE HAVING A VARIABLE REDISTRIBUTION LAYER THICKNESS

VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE

ELECTRONIC DEVICE INCLUDING REDISTRIBUTION LAYER PAD HAVING A VOID

WAFER LEVEL PACKAGE STRUCTURE WITH INTERNAL CONDUCTIVE LAYER

INTERPOSER WITH CONDUCTIVE ROUTING EXPOSED ON SIDEWALLS

System-in-Package Devices and Methods for Forming System-in-Package...

Electrical device and a method for forming an electrical device

PACKAGE STACKING USING CHIP TO WAFER BONDING

METHOD FOR PRODUCING PACKAGED MEMS ASSEMBLIES AT THE WAFER LEVEL, A...

MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DIS...

ROBUST INTERMETALLIC COMPOUND LAYER INTERFACE FOR PACKAGE IN PACKAG...

LOW THERMAL RESISTANCE HANGING DIE PACKAGE

ADVANCED NODE COST REDUCTION BY ESD INTERPOSER

MICROELECTROMECHANICAL SYSTEM (MEMS) ON APPLICATION SPECIFIC INTEGR...