Christine Hau-Riege

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout construction for addressing electromigration
- Patent number 11,508,725
- Issue date Nov 22, 2022
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,600,785
- Issue date Mar 24, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,972,624
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods to reduce parasitic capacitance
- Patent number 9,941,156
- Issue date Apr 10, 2018
- QUALCOMM Incorporated
- Shiqun Gu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked redistribution layers on die
- Patent number 9,171,782
- Issue date Oct 27, 2015
- QUALCOMM Incorporated
- Christine Sung-An Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper interconnects with improved electromigration lifetime
- Patent number 8,723,321
- Issue date May 13, 2014
- GLOBALFOUNDIES Inc.
- Christy Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive sidewall for microbumps
- Patent number 8,482,125
- Issue date Jul 9, 2013
- QUALCOMM Incorporated
- Arvind Chandrasekaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for quantitative detection of multiple electromigration fail...
- Patent number 7,818,655
- Issue date Oct 19, 2010
- Advanced Micro Devices, Inc.
- Eun-Joo Lee
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit design system
- Patent number 7,451,411
- Issue date Nov 11, 2008
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of making a semiconductor device that has copper damascene i...
- Patent number 7,153,774
- Issue date Dec 26, 2006
- Intel Corporation
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of an interconnect
- Patent number 7,135,775
- Issue date Nov 14, 2006
- Intel Corporation
- Stephen T. Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor component and method for precluding stress-induced vo...
- Patent number 7,026,225
- Issue date Apr 11, 2006
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for determining electromigration and interlayer diel...
- Patent number 6,897,476
- Issue date May 24, 2005
- Advanced Micro Devices, Inc.
- Hyeon-Seag Kim
- G01 - MEASURING TESTING
Information Patent Grant
Wafer-bonding using solder and method of making the same
- Patent number 6,870,262
- Issue date Mar 22, 2005
- Intel Corporation
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for current-enhanced stress-migration testing of...
- Patent number 6,867,056
- Issue date Mar 15, 2005
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Interconnect test structure with slotted feeder lines to prevent st...
- Patent number 6,822,437
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Determination of permeability of layer material within interconnect
- Patent number 6,822,473
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Method of forming SiC capped copper interconnects with reduced hill...
- Patent number 6,818,557
- Issue date Nov 16, 2004
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
System and method for determining location of extrusion in intercon...
- Patent number 6,768,323
- Issue date Jul 27, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Structure, system, and method for assessing electromigration permea...
- Patent number 6,762,597
- Issue date Jul 13, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Method for assessing the reliability of interconnects
- Patent number 6,725,433
- Issue date Apr 20, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Methodology for an assessment of the degree of barrier permeability...
- Patent number 6,714,037
- Issue date Mar 30, 2004
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G01 - MEASURING TESTING
Information Patent Grant
Wafer-bonding using solder and method of making the same
- Patent number 6,667,225
- Issue date Dec 23, 2003
- Intel Corporation
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement of an interconnect
- Patent number 6,518,184
- Issue date Feb 11, 2003
- Intel Corporation
- Stephen T. Chambers
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20200168604
- Publication date May 28, 2020
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAND GRID BASED MULTI SIZE PAD PACKAGE
- Publication number 20190043817
- Publication date Feb 7, 2019
- QUALCOMM Incorporated
- Manoj KADADE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20180211957
- Publication date Jul 26, 2018
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAND GRID BASED MULTI SIZE PAD PACKAGE
- Publication number 20180053740
- Publication date Feb 22, 2018
- QUALCOMM Incorporated
- Manoj KAKADE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE
- Publication number 20160293475
- Publication date Oct 6, 2016
- QUALCOMM Incorporated
- Shiqun Gu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20150054568
- Publication date Feb 26, 2015
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED REDISTRIBUTION LAYERS ON DIE
- Publication number 20150041982
- Publication date Feb 12, 2015
- QUALCOMM Incorporated
- Christine Sung-An Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE SIDEWALL FOR MICROBUMPS
- Publication number 20130105559
- Publication date May 2, 2013
- QUALCOMM Incorporated
- Arvind Chandrasekaran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit design system
- Publication number 20070300200
- Publication date Dec 27, 2007
- Advanced Micro Devices, Inc.
- Christine Hau-Riege
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Copper interconnects with improved electromigration lifetime
- Publication number 20070284748
- Publication date Dec 13, 2007
- Advanced Micro Devices, Inc.
- Christy Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS C...
- Publication number 20070278484
- Publication date Dec 6, 2007
- Frank Feustel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-bonding using solder and method of making the same
- Publication number 20040056073
- Publication date Mar 25, 2004
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making a semiconductor device that has copper damascene i...
- Publication number 20030228753
- Publication date Dec 11, 2003
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making a semiconductor device that has copper damascene i...
- Publication number 20030194857
- Publication date Oct 16, 2003
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhancement of an interconnect
- Publication number 20030137050
- Publication date Jul 24, 2003
- Stephen T. Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Wafer-bonding using solder and method of making the same
- Publication number 20030113976
- Publication date Jun 19, 2003
- Stefan Hau-Riege
- H01 - BASIC ELECTRIC ELEMENTS

Christine Hau-Riege

Person

Patents Grantslast 30 patents

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Systems and methods to reduce parasitic capacitance

Stacked redistribution layers on die

Copper interconnects with improved electromigration lifetime

Conductive sidewall for microbumps

Method for quantitative detection of multiple electromigration fail...

Integrated circuit design system

Method of making a semiconductor device that has copper damascene i...

Enhancement of an interconnect

Semiconductor component and method for precluding stress-induced vo...

Test structure for determining electromigration and interlayer diel...

Wafer-bonding using solder and method of making the same

System and method for current-enhanced stress-migration testing of...

Interconnect test structure with slotted feeder lines to prevent st...

Determination of permeability of layer material within interconnect

Method of forming SiC capped copper interconnects with reduced hill...

System and method for determining location of extrusion in intercon...

Structure, system, and method for assessing electromigration permea...

Method for assessing the reliability of interconnects

Methodology for an assessment of the degree of barrier permeability...

Wafer-bonding using solder and method of making the same

Enhancement of an interconnect

Patents Applicationslast 30 patents

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAND GRID BASED MULTI SIZE PAD PACKAGE

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAND GRID BASED MULTI SIZE PAD PACKAGE

SYSTEMS AND METHODS TO REDUCE PARASITIC CAPACITANCE

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

STACKED REDISTRIBUTION LAYERS ON DIE

CONDUCTIVE SIDEWALL FOR MICROBUMPS

Integrated circuit design system

Copper interconnects with improved electromigration lifetime

METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS C...

Wafer-bonding using solder and method of making the same

Method of making a semiconductor device that has copper damascene i...

Method of making a semiconductor device that has copper damascene i...

Enhancement of an interconnect

Wafer-bonding using solder and method of making the same