Christopher J. Pettey

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device adapted to send information in accordance with a communicati...
- Patent number 7,587,542
- Issue date Sep 8, 2009
- Hewlett-Packard Development Company, L.P.
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device operating according to a communication protocol
- Patent number 7,464,207
- Issue date Dec 9, 2008
- Hewlett-Packard Development Company, L.P.
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed peripheral interconnect apparatus, method and system
- Patent number 7,099,986
- Issue date Aug 29, 2006
- Hewlett-Packard Development Company, L.P.
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with registered peripheral component interconnect d...
- Patent number 6,816,934
- Issue date Nov 9, 2004
- Hewlett-Packard Development Company, L.P.
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priority transaction support on the PCI-X bus
- Patent number 6,801,970
- Issue date Oct 5, 2004
- Hewlett-Packard Development Company, L.P.
- Dwight D. Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed peripheral interconnect apparatus, method and system
- Patent number 6,557,068
- Issue date Apr 29, 2003
- Hewlett-Packard Development Company, LP
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number RE37980
- Issue date Feb 4, 2003
- Compaq Computer Corporation
- Bassam Elkhoury
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
High speed peripheral interconnect apparatus, method and system
- Patent number 6,266,731
- Issue date Jul 24, 2001
- Compaq Computer Corporation
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number 6,148,359
- Issue date Nov 14, 2000
- Compaq Computer Corporation
- Bassam Elkhoury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller supporting DRAM circuits with different operating...
- Patent number 6,134,638
- Issue date Oct 17, 2000
- Compaq Computer Corporation
- S. Paul Olarig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lock protocol for PCI bus using an additional "superlock" signal on...
- Patent number 6,098,134
- Issue date Aug 1, 2000
- Compaq Computer Corp.
- Peter Michels
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus agent including a storage medium between a data bus and th...
- Patent number 6,067,590
- Issue date May 23, 2000
- Compaq Computer Corporation
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bridge circuit comprising independent transaction buffers with cont...
- Patent number 6,055,590
- Issue date Apr 25, 2000
- Compaq Computer Corporation
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aligning a memory read request with a cache line boundary when the...
- Patent number 6,021,480
- Issue date Feb 1, 2000
- Compaq Computer Corporation
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Receiving a write request that allows less than one cache line of d...
- Patent number 5,903,906
- Issue date May 11, 1999
- Compaq Computer Corporation
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing data from a bridge to a requesting device while the bridg...
- Patent number 5,872,941
- Issue date Feb 16, 1999
- Compaq Computer Corp.
- Alan L. Goodrum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delayed transaction protocol for computer system bus
- Patent number 5,870,567
- Issue date Feb 9, 1999
- Compaq Computer Corporation
- Brian S. Hausauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-to-bus bridge in computer system, with fast burst memory range
- Patent number 5,835,741
- Issue date Nov 10, 1998
- Compaq Computer Corporation
- Bassam Elkhoury
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
High speed peripheral interconnect apparatus, method and system
- Publication number 20060031621
- Publication date Feb 9, 2006
- Compaq Computer Corporation
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed peripheral interconnect apparatus, method and system
- Publication number 20050273534
- Publication date Dec 8, 2005
- Compaq Computer Corporation
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed peripheral interconnect apparatus, method and system
- Publication number 20050033893
- Publication date Feb 10, 2005
- Compaq Computer Corporation
- Christopher J. Pettey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed peripheral interconnect apparatus, method and system
- Publication number 20030225956
- Publication date Dec 4, 2003
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Priority transaction support on the PCI-X bus
- Publication number 20030065842
- Publication date Apr 3, 2003
- Dwight D. Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed peripheral interconnect apparatus, method and system
- Publication number 20020073258
- Publication date Jun 13, 2002
- Compaq Computer Corporation
- Dwight Riley
- G06 - COMPUTING CALCULATING COUNTING

Christopher J. Pettey

Person

Patents Grantslast 30 patents

Device adapted to send information in accordance with a communicati...

Device operating according to a communication protocol

High speed peripheral interconnect apparatus, method and system

Computer system with registered peripheral component interconnect d...

Priority transaction support on the PCI-X bus

High speed peripheral interconnect apparatus, method and system

Bus-to-bus bridge in computer system, with fast burst memory range

High speed peripheral interconnect apparatus, method and system

Bus-to-bus bridge in computer system, with fast burst memory range

Memory controller supporting DRAM circuits with different operating...

Lock protocol for PCI bus using an additional "superlock" signal on...

Data bus agent including a storage medium between a data bus and th...

Bridge circuit comprising independent transaction buffers with cont...

Aligning a memory read request with a cache line boundary when the...

Receiving a write request that allows less than one cache line of d...

Providing data from a bridge to a requesting device while the bridg...

Delayed transaction protocol for computer system bus

Bus-to-bus bridge in computer system, with fast burst memory range

Patents Applicationslast 30 patents

High speed peripheral interconnect apparatus, method and system

High speed peripheral interconnect apparatus, method and system

High speed peripheral interconnect apparatus, method and system

High speed peripheral interconnect apparatus, method and system

Priority transaction support on the PCI-X bus

High speed peripheral interconnect apparatus, method and system