Chun Jiang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Zero power memory cell with reduced threshold voltage
- Patent number 6,737,702
- Issue date May 18, 2004
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming uniformly planarized structure in a semiconductor...
- Patent number 6,689,697
- Issue date Feb 10, 2004
- Advanced Micro Devices, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zero power memory cell with improved data retention
- Patent number 6,660,579
- Issue date Dec 9, 2003
- Lattice Semiconductor Corp.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM device having improved data retention and process for fabric...
- Patent number 6,649,514
- Issue date Nov 18, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM with a neutralized doping at tunnel window edge
- Patent number 6,600,188
- Issue date Jul 29, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect methodology employing a low dielectric constant etch s...
- Patent number 6,593,632
- Issue date Jul 15, 2003
- Advanced Micro Devices, Inc.
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM tunnel window for program injection via P+ contacted...
- Patent number 6,545,313
- Issue date Apr 8, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eeprom tunnel window for program injection via P+ contacted...
- Patent number 6,455,375
- Issue date Sep 24, 2002
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective air gap insulation
- Patent number 6,440,839
- Issue date Aug 27, 2002
- Advanced Micro Devices, Inc.
- Hamid Partovi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for measuring gate length and drain/source gate overlap
- Patent number 6,166,558
- Issue date Dec 26, 2000
- Advanced Micro Devices, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce gate-to-local interconnect capacitance using a low...
- Patent number 6,137,126
- Issue date Oct 24, 2000
- Advanced Micro Devices, Inc.
- Steven C. Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Model for taking into account gate resistance induced propagation d...
- Patent number 6,110,219
- Issue date Aug 29, 2000
- Advanced Micro Devices, Inc.
- Chun Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for designing and manufacturing CMOS inverters by estimating...
- Patent number 6,099,576
- Issue date Aug 8, 2000
- Advanced Micro Devices, Inc.
- Chun Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
C-V method to extract lateral channel doping profiles of MOSFETs
- Patent number 6,069,485
- Issue date May 30, 2000
- Advanced Micro Devices, Inc.
- Wei Long
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for providing an interconnect layout to reduce de...
- Patent number 5,986,477
- Issue date Nov 16, 1999
- Advanced Micro Devices, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric S/D structure to improve transistor performance by reduc...
- Patent number 5,925,914
- Issue date Jul 20, 1999
- Advanced Micro Devices
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric drain/source layout for robust electrostatic discharge p...
- Patent number 5,714,785
- Issue date Feb 3, 1998
- VLSI Technology, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-well resistor as a ballast resistor for output MOSFET
- Patent number 5,712,200
- Issue date Jan 27, 1998
- VLSI Technology, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-well resistor as a ballast resistor for output MOSFET
- Patent number 5,637,902
- Issue date Jun 10, 1997
- VLSI Technology, Inc.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing hot carrier induced degradation to fall and rise time of CM...
- Patent number 5,587,665
- Issue date Dec 24, 1996
- VLSI Technology, Inc.
- Chun Jiang
- G01 - MEASURING TESTING
Information Patent Grant
AC drain voltage charging source for PROM devices
- Patent number 5,339,270
- Issue date Aug 16, 1994
- VLSI Technology, Inc.
- Chun Jiang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Polycide fuse with reduced programming time
- Publication number 20070111403
- Publication date May 17, 2007
- Chun Jiang
- G11 - INFORMATION STORAGE
Information Patent Application
Diode with low junction capacitance
- Publication number 20060125014
- Publication date Jun 15, 2006
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Zero power memory cell with reduced threshold voltage

Method of forming uniformly planarized structure in a semiconductor...

Zero power memory cell with improved data retention

EEPROM device having improved data retention and process for fabric...

EEPROM with a neutralized doping at tunnel window edge

Interconnect methodology employing a low dielectric constant etch s...

EEPROM tunnel window for program injection via P&#x0002B; contacted...

Eeprom tunnel window for program injection via P&#x0002B; contacted...

Selective air gap insulation

Method for measuring gate length and drain/source gate overlap

Method to reduce gate-to-local interconnect capacitance using a low...

Model for taking into account gate resistance induced propagation d...

System for designing and manufacturing CMOS inverters by estimating...

C-V method to extract lateral channel doping profiles of MOSFETs

Method and system for providing an interconnect layout to reduce de...

Asymmetric S/D structure to improve transistor performance by reduc...

Asymmetric drain/source layout for robust electrostatic discharge p...

N-well resistor as a ballast resistor for output MOSFET

N-well resistor as a ballast resistor for output MOSFET

Testing hot carrier induced degradation to fall and rise time of CM...

AC drain voltage charging source for PROM devices

Patents Applicationslast 30 patents

Polycide fuse with reduced programming time

Diode with low junction capacitance

EEPROM tunnel window for program injection via P+ contacted...

Eeprom tunnel window for program injection via P+ contacted...