Chung Chyung Han

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,768,144
- Issue date Sep 19, 2017
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,391,045
- Issue date Jul 12, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,257,410
- Issue date Feb 9, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,034,730
- Issue date May 19, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power/ground layout for chips
- Patent number 8,946,890
- Issue date Feb 3, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laterally diffused metal oxide semiconductor (LDMOS) device with ov...
- Patent number 8,921,938
- Issue date Dec 30, 2014
- Marvell International Ltd.
- Xin Yi Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS structure having a gate without spacers
- Patent number 6,127,710
- Issue date Oct 3, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mosfet with raised source and drain regions
- Patent number 6,063,676
- Issue date May 16, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density MOSFET with raised source and drain regions
- Patent number 6,043,129
- Issue date Mar 28, 2000
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving latch-up immunity and interwell isolation in a...
- Patent number 6,017,785
- Issue date Jan 25, 2000
- Integrated Device Technology, Inc.
- Chung-Chyung Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for improving latch-up immunity and interwell isolation i...
- Patent number 5,831,313
- Issue date Nov 3, 1998
- Integrated Device Technology, Inc.
- Chung-Chyung Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for controlling threshold voltage of MOSFET
- Patent number 5,793,088
- Issue date Aug 11, 1998
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a CMOS device
- Patent number 5,750,424
- Issue date May 12, 1998
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a CMOS device
- Patent number 5,654,213
- Issue date Aug 5, 1997
- Integrated Device Technology, Inc.
- Jeong Yeol Choi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...
- Publication number 20160155732
- Publication date Jun 2, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20150279806
- Publication date Oct 1, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20150155202
- Publication date Jun 4, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20140124961
- Publication date May 8, 2014
- Marvell World Trade Ltd.
- Albert WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20120098127
- Publication date Apr 26, 2012
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186960
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20110186992
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186998
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS

Chung Chyung Han

Person

Patents Grantslast 30 patents

Package assembly including a semiconductor substrate in which a fir...

Recessed semiconductor substrates and associated techniques

Package assembly including a semiconductor substrate in which a fir...

Recessed semiconductor substrates and associated techniques

Power/ground layout for chips

Laterally diffused metal oxide semiconductor (LDMOS) device with ov...

CMOS structure having a gate without spacers

Mosfet with raised source and drain regions

High density MOSFET with raised source and drain regions

Method for improving latch-up immunity and interwell isolation in a...

Structure for improving latch-up immunity and interwell isolation i...

Structure for controlling threshold voltage of MOSFET

Method for fabricating a CMOS device

Method for fabricating a CMOS device

Patents Applicationslast 30 patents

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

POWER/GROUND LAYOUT FOR CHIPS

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

POWER/GROUND LAYOUT FOR CHIPS

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

RECESSED SEMICONDUCTOR SUBSTRATES