Chung Woh Lai

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Dislocation engineering using a scanned laser
- Patent number 8,865,571
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation engineering using a scanned laser
- Patent number 8,865,572
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor top plate over source/drain to form a 1T memory device
- Patent number 8,716,081
- Issue date May 6, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer-less low-K dielectric processes
- Patent number 8,624,329
- Issue date Jan 7, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid orientation substrate with stress layer
- Patent number 8,274,115
- Issue date Sep 25, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming p-channel field effect transistors having SiGe s...
- Patent number 8,198,194
- Issue date Jun 12, 2012
- Samsung Electronics Co., Ltd.
- Jong Ho Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming shallow trench isolation structures for integrate...
- Patent number 8,178,417
- Issue date May 15, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 8,143,651
- Issue date Mar 27, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation engineering using a scanned laser
- Patent number 8,138,066
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture of an integrated circuit system with self-ali...
- Patent number 8,053,327
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to remove spacer after salicidation to enhance contact etch...
- Patent number 7,999,325
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Young Way Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell structure and method for fabrication thereof
- Patent number 7,999,300
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Zhao Lun
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and apparatus for post silicide spacer removal
- Patent number 7,977,185
- Issue date Jul 12, 2011
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor fabrication process including an SiGe rework method
- Patent number 7,955,936
- Issue date Jun 7, 2011
- Chartered Semiconductor Manufacturing Ltd.
- Yong Siang Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress optimization in dual embedded epitaxially grown semiconducto...
- Patent number 7,935,593
- Issue date May 3, 2011
- Samsung Electronics Co., Ltd.
- Jong Ho Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having a plurality of MOSFET devices
- Patent number 7,932,178
- Issue date Apr 26, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of manufacturing semiconductor devices and structures thereof
- Patent number 7,838,372
- Issue date Nov 23, 2010
- Infineon Technologies AG
- Jin-Ping Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system employing selective epitaxial growth tech...
- Patent number 7,795,680
- Issue date Sep 14, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 7,767,577
- Issue date Aug 3, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer-less low-k dielectric processes
- Patent number 7,615,427
- Issue date Nov 10, 2009
- Chartered Semiconductor Manufacturing, Ltd.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to remove spacer after salicidation to enhance contact etch...
- Patent number 7,445,978
- Issue date Nov 4, 2008
- Chartered Semiconductor Manufacturing, Ltd.
- Young Way Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite stress spacer
- Patent number 7,256,084
- Issue date Aug 14, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Khee Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of cobalt silicidation using an oxide-Titanium interlayer
- Patent number 6,653,227
- Issue date Nov 25, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal stability improvement of CoSi2 film by stuffing in titanium
- Patent number 6,383,922
- Issue date May 7, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Bei Chao Zhang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DISLOCATION ENGINEERING USING A SCANNED LASER
- Publication number 20140154872
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISLOCATION ENGINEERING USING A SCANNED LASER
- Publication number 20140154873
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation Engineering Using a Scanned Laser
- Publication number 20120294322
- Publication date Nov 22, 2012
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation Engineering Using a Scanned Laser
- Publication number 20120138823
- Publication date Jun 7, 2012
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming P-Channel Field Effect Transistors Having SiGe S...
- Publication number 20110237039
- Publication date Sep 29, 2011
- Jong-Ho Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20100301424
- Publication date Dec 2, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTO...
- Publication number 20100197093
- Publication date Aug 5, 2010
- Samsung Electronics Co., Ltd.
- Jong Ho Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF
- Publication number 20100187587
- Publication date Jul 29, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Zhao LUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISLOCATION ENGINEERING USING A SCANNED LASER
- Publication number 20100081259
- Publication date Apr 1, 2010
- International Business Machines Corporation
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spacer-less Low-K Dielectric Processes
- Publication number 20100059831
- Publication date Mar 11, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...
- Publication number 20100009527
- Publication date Jan 14, 2010
- Chartered Semiconductor Manufacturing LTD.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Fabrication Process Including An SiGe Rework Method
- Publication number 20100009502
- Publication date Jan 14, 2010
- Yong Siang Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Manufacturing Semiconductor Devices and Structures Thereof
- Publication number 20090289379
- Publication date Nov 26, 2009
- Jin-Ping Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...
- Publication number 20090261448
- Publication date Oct 22, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shailendra MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER
- Publication number 20090236663
- Publication date Sep 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20090206408
- Publication date Aug 20, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS
- Publication number 20090146181
- Publication date Jun 11, 2009
- Chartered Semiconductor Manufacturing LTD.
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...
- Publication number 20090146262
- Publication date Jun 11, 2009
- Chartered Semiconductor Manufacturing LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained Semiconductor Device and Method of Making Same
- Publication number 20090050972
- Publication date Feb 26, 2009
- Richard Lindsay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH...
- Publication number 20090026549
- Publication date Jan 29, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Young Way Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS
- Publication number 20080315317
- Publication date Dec 25, 2008
- Chartered Semiconductor Manufacturing LTD.
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE
- Publication number 20080224228
- Publication date Sep 18, 2008
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES
- Publication number 20080157223
- Publication date Jul 3, 2008
- Chartered Semiconductor Manufacturing LTD.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH ISOLATION
- Publication number 20080150074
- Publication date Jun 26, 2008
- Chartered Semiconductor Manufacturing LTD.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spacer-less low-k dielectric processes
- Publication number 20070281410
- Publication date Dec 6, 2007
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL
- Publication number 20070161244
- Publication date Jul 12, 2007
- International Business Machines Corporation
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Composite stress spacer
- Publication number 20060252194
- Publication date Nov 9, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Khee Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to remove spacer after salicidation to enhance contact etch...
- Publication number 20060249794
- Publication date Nov 9, 2006
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Young Way Teh
- H01 - BASIC ELECTRIC ELEMENTS

Chung Woh Lai

Person

Patents Grantslast 30 patents

Dislocation engineering using a scanned laser

Dislocation engineering using a scanned laser

Capacitor top plate over source/drain to form a 1T memory device

Spacer-less low-K dielectric processes

Hybrid orientation substrate with stress layer

Methods of forming p-channel field effect transistors having SiGe s...

Method of forming shallow trench isolation structures for integrate...

Nested and isolated transistors with reduced impedance difference

Dislocation engineering using a scanned laser

Method of manufacture of an integrated circuit system with self-ali...

Method to remove spacer after salicidation to enhance contact etch...

Memory cell structure and method for fabrication thereof

Method and apparatus for post silicide spacer removal

Semiconductor fabrication process including an SiGe rework method

Stress optimization in dual embedded epitaxially grown semiconducto...

Integrated circuit having a plurality of MOSFET devices

Methods of manufacturing semiconductor devices and structures thereof

Integrated circuit system employing selective epitaxial growth tech...

Nested and isolated transistors with reduced impedance difference

Spacer-less low-k dielectric processes

Method to remove spacer after salicidation to enhance contact etch...

Composite stress spacer

Method of cobalt silicidation using an oxide-Titanium interlayer

Thermal stability improvement of CoSi2 film by stuffing in titanium

Patents Applicationslast 30 patents

DISLOCATION ENGINEERING USING A SCANNED LASER

DISLOCATION ENGINEERING USING A SCANNED LASER

Dislocation Engineering Using a Scanned Laser

Dislocation Engineering Using a Scanned Laser

Methods of Forming P-Channel Field Effect Transistors Having SiGe S...

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTO...

MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF

DISLOCATION ENGINEERING USING A SCANNED LASER

Spacer-less Low-K Dielectric Processes

INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...

Semiconductor Fabrication Process Including An SiGe Rework Method

Methods of Manufacturing Semiconductor Devices and Structures Thereof

METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...

HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS

INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...

Strained Semiconductor Device and Method of Making Same

METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH...

SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS

CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE

INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES

INTEGRATED CIRCUIT SYSTEM WITH ISOLATION

Spacer-less low-k dielectric processes

METHOD AND APPARATUS FOR POST SILICIDE SPACER REMOVAL

Composite stress spacer

Method to remove spacer after salicidation to enhance contact etch...