BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which:
FIG. 1A illustrates a partially processed MOSFET 100 after a silicidation and prior to removal of the nitride spacer according to an exemplary embodiment of the present invention;
FIG. 1B illustrates a partially processed MOSFET 100 after the nitride spacer has been removed using a method of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 2 depicts a flow diagram of a method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3A illustrates processing of a MOSFET 300 (similar to the MOSFET 100 depicted in FIG. 1) in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3B illustrates deposition of an oxide layer 307 in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3C illustrates deposition of a nitride layer 308 in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3D illustrates etching of the nitride layer 308 in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3E illustrates etching of the oxide layer 307 in the method 200 of post suicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3F illustrates etching the nitride from the wafer in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3G illustrates reactive ion etching (RIE) of the spacer 302 in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention;
FIG. 3H illustrates depositing a stressed nitride layer 314 over the wafer 300 in the method 200 of post silicide spacer removal according to an exemplary embodiment of the present invention; and
FIG. 4 depicts a block diagram illustrating a system 400 for post silicide spacer removal according to an exemplary embodiment of the present invention.