Cyrus Afghahi

Person

Aliso Viejo, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Block redundancy implementation in heirarchical ram's
- Patent number 7,567,482
- Issue date Jul 28, 2009
- Broadcom Corporation
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block redundancy implementation in heirarchical RAM'S
- Patent number 7,177,225
- Issue date Feb 13, 2007
- Broadcom Corporation
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed, highly configurable modular predecoding
- Patent number 6,898,145
- Issue date May 24, 2005
- Broadcom Corporation
- Gil I. Winograd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having simultaneous read/write and refresh operations...
- Patent number 6,888,761
- Issue date May 3, 2005
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed, highly configurable modular predecoding
- Patent number 6,760,243
- Issue date Jul 6, 2004
- Broadcom Corporation
- Gil I. Winograd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent continuous refresh RAM cell architecture
- Patent number 6,717,863
- Issue date Apr 6, 2004
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Grant
Block redundancy implementation in heirarchical RAM's
- Patent number 6,714,467
- Issue date Mar 30, 2004
- Broadcom Corporation
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit capable of simultaneous writing and refreshing on th...
- Patent number 6,600,677
- Issue date Jul 29, 2003
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced leakage memory cell
- Patent number 6,574,136
- Issue date Jun 3, 2003
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Grant
Transparent continuous refresh RAM cell architecture
- Patent number 6,430,098
- Issue date Aug 6, 2002
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S
- Publication number 20090316512
- Publication date Dec 24, 2009
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S
- Publication number 20070109886
- Publication date May 17, 2007
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed, highly configurable modular predecoding
- Publication number 20040208037
- Publication date Oct 21, 2004
- Gil I. Winograd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transparent continuous refresh RAM cell architecture
- Publication number 20040184335
- Publication date Sep 23, 2004
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Application
Block redundancy implementation in heirarchical RAM'S
- Publication number 20040120202
- Publication date Jun 24, 2004
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transparent continuous refresh RAM cell architecture
- Publication number 20030202384
- Publication date Oct 30, 2003
- Broadcom Corporation
- Cyrus Afghahi
- G11 - INFORMATION STORAGE
Information Patent Application
Block redundancy implementation in heirarchical RAM's
- Publication number 20030179641
- Publication date Sep 25, 2003
- Esin Terzioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Distributed, highly configurable modular predecoding
- Publication number 20030179642
- Publication date Sep 25, 2003
- Gil I. Winograd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transparent continuous refresh ram cell architecture
- Publication number 20020057617
- Publication date May 16, 2002
- Cyrus Afghahi
- G11 - INFORMATION STORAGE

Cyrus Afghahi

Person

Patents Grantslast 30 patents

Block redundancy implementation in heirarchical ram's

Block redundancy implementation in heirarchical RAM'S

Distributed, highly configurable modular predecoding

Memory device having simultaneous read/write and refresh operations...

Distributed, highly configurable modular predecoding

Transparent continuous refresh RAM cell architecture

Block redundancy implementation in heirarchical RAM&#x00027;s

Memory circuit capable of simultaneous writing and refreshing on th...

Reduced leakage memory cell

Transparent continuous refresh RAM cell architecture

Patents Applicationslast 30 patents

BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S

BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S

Distributed, highly configurable modular predecoding

Transparent continuous refresh RAM cell architecture

Block redundancy implementation in heirarchical RAM'S

Transparent continuous refresh RAM cell architecture

Block redundancy implementation in heirarchical RAM's

Distributed, highly configurable modular predecoding

Transparent continuous refresh ram cell architecture

Block redundancy implementation in heirarchical RAM's