Claims
- 1. A hierarchical memory structure, comprising:
a first predecoder adapted to perform a first layer of address predecoding; and at least one second predecoder interacting with said first predecoder and adapted to perform a second layer of address predecoding.
- 2. The memory structure of claim 1, wherein said second predecoder is located proximate a local sense amplifier.
- 3. The memory structure of claim 1, wherein said second predecoder is adapted to vary from memory architecture to memory architecture.
- 4. The memory structure of claim 1, wherein said first predecoder circuit is located proximate a global sense amplifier.
- 5. The memory structure of claim 1, wherein said first predecoder is adapted to vary little from memory architecture to memory architecture.
- 6. The memory structure of claim 1, wherein an input to said second predecoder is an output from said first predecoder.
- 7. The memory structure of claim 6, wherein said input to said second predecoder is at least one buffered address line.
- 8. The memory structure of claim 1, further comprising at least one decoder communicating with at least said second predecoder.
- 9. The memory structure of claim 7, further comprising at least one wordline coupled to at least said decoder.
- 10. A hierarchical memory structure, comprising:
a first predecoder including block select information; at least two second predecoders interacting with at least said first predecoder; and at least one decoder adapted to interact with at least said second predecoders.
- 11. The memory structure of claim 10, wherein said first predecoder is adapted to perform a first layer of address predecoding.
- 12. The memory structure of claim 10, wherein said second predecoders are adapted to perform a second layer of predecoding.
- 13. A memory device comprising:
a synchronous controlled global element comprising a global predecoder; and a self-timed local element comprising at least one local predecoder interfacing with said synchronous controlled global element.
- 14. The memory device of claim 13, wherein said global element further comprises at least one global decoder.
- 15. The memory device of claim 13, wherein said global element further comprises at least one global controller.
- 16. The memory device of claim 13, wherein said global element further comprises at least one global sense amplifier.
- 17. The memory device of claim 13, wherein said local element further comprises a plurality of memory cells forming at least one cell array.
- 18. A hierarchical memory structure, comprising:
a first area adapted to receive predecoder circuitry that varies little from memory to memory; and a second area adapted to receive predecoder circuitry.
- 19. The hierarchical memory structure of claim 18, including a third area adapted to receive predecoder circuitry.
- 20. The hierarchical memory structure of claim 18, including a plurality of areas adapted to receive predecoder circuits.
- 21. The memory architecture of claim 18, wherein said first area is defined by at least a global decoder and at least a global sense amplifier.
- 22. The memory architecture of claim 18, wherein said second area is defined by at least one local sense amplifier.
- 23. A method of optimizing predecoder circuitry distribution in a structure, comprising locating predecoder circuitry that varies little from structure to structure in the structure separate from other predecoder circuitry that varies from structure to structure.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of, and claims benefit of and priority from, application Ser. No. 10/100,757 Filled Mar. 19, 2002, titled “Synchronous Controlled, Self-Timed Local SRAM Block”, the complete subject matter of which is incorporated herein by reference in its entirety.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10100757 |
Mar 2002 |
US |
Child |
10177001 |
Jun 2002 |
US |