Darrell Rinerson

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 11,672,189
- Issue date Jun 6, 2023
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 11,502,249
- Issue date Nov 15, 2022
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 11,398,256
- Issue date Jul 26, 2022
- Unity Semiconductor Corporation
- Chang Hua Siau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 11,063,214
- Issue date Jul 13, 2021
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,833,125
- Issue date Nov 10, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,797,106
- Issue date Oct 6, 2020
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 10,680,171
- Issue date Jun 9, 2020
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 10,622,028
- Issue date Apr 14, 2020
- Unity Semiconductor Corporation
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 10,340,312
- Issue date Jul 2, 2019
- Hefei Reliance Memory Limited
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 10,224,480
- Issue date Mar 5, 2019
- Hefei Reliance Memory Limited
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 10,002,646
- Issue date Jun 19, 2018
- Unity Semiconductor Corporation
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Grant
Low read current architecture for memory
- Patent number 9,837,149
- Issue date Dec 5, 2017
- Unity Semiconductor Corporation
- Bruce Lynn Bateman
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 9,831,425
- Issue date Nov 28, 2017
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,806,130
- Issue date Oct 31, 2017
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,570,515
- Issue date Feb 14, 2017
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Low read current architecture for memory
- Patent number 9,368,200
- Issue date Jun 14, 2016
- Unity Semiconductor Corporation
- Bruce Lynn Bateman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 9,159,408
- Issue date Oct 13, 2015
- Unity Semiconductor Corporation
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-terminal reversibly switchable memory device
- Patent number 9,159,913
- Issue date Oct 13, 2015
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 8,897,050
- Issue date Nov 25, 2014
- Unity Semiconductor Corporation
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Grant
Low read current architecture for memory
- Patent number 8,737,151
- Issue date May 27, 2014
- Unity Semiconductor Corporation
- Bruce Bateman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element with a reactive metal layer
- Patent number 8,675,389
- Issue date Mar 18, 2014
- Unity Semiconductor Corporation
- Christophe Chevallier
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating multi-resistive state memory devices
- Patent number 8,611,130
- Issue date Dec 17, 2013
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Device fabrication
- Patent number 8,569,160
- Issue date Oct 29, 2013
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold device for a memory array
- Patent number 8,395,928
- Issue date Mar 12, 2013
- Unity Semiconductor Corporation
- Julie Casperson Brewer
- G11 - INFORMATION STORAGE
Information Patent Grant
Device fabrication
- Patent number 8,314,024
- Issue date Nov 20, 2012
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Local bit lines and methods of selecting the same to access memory...
- Patent number 8,270,193
- Issue date Sep 18, 2012
- Unity Semiconductor Corporation
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device using ion implant isolated conductive metal oxide
- Patent number 8,268,667
- Issue date Sep 18, 2012
- Unity Semiconductor Corporation
- Darrell Rinerson
- F04 - POSITIVE DISPLACEMENT MACHINES FOR LIQUIDS PUMPS FOR LIQUIDS OR ELASTIC...
Information Patent Grant
Continuous plane of thin-film materials for a two-terminal cross-po...
- Patent number 8,237,142
- Issue date Aug 7, 2012
- Unity Semiconductor Corporation
- Robin Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating multi-resistive state memory devices
- Patent number 8,062,942
- Issue date Nov 22, 2011
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Grant
Low read current architecture for memory
- Patent number 8,031,545
- Issue date Oct 4, 2011
- Unity Semiconductor Corporation
- Darrell Rinerson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20210193917
- Publication date Jun 24, 2021
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20210013262
- Publication date Jan 14, 2021
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20200302973
- Publication date Sep 24, 2020
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20200259079
- Publication date Aug 13, 2020
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20190305047
- Publication date Oct 3, 2019
- Hefei Reliance Memory Limited
- Christophe J. CHEVALLIER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20190173006
- Publication date Jun 6, 2019
- Hefei Reliance Memory Limited
- Darrell RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20180342268
- Publication date Nov 29, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20180130946
- Publication date May 10, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20180122857
- Publication date May 3, 2018
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20170179197
- Publication date Jun 22, 2017
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
LOW READ CURRENT ARCHITECTURE FOR MEMORY
- Publication number 20160372189
- Publication date Dec 22, 2016
- UNITY SEMICONDUCTOR CORPORATION
- Bruce Lynn Bateman
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENT WITH A REACTIVE METAL LAYER
- Publication number 20160005793
- Publication date Jan 7, 2016
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20150380642
- Publication date Dec 31, 2015
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20150132917
- Publication date May 14, 2015
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Application
TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
- Publication number 20150029780
- Publication date Jan 29, 2015
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
LOW READ CURRENT ARCHITECTURE FOR MEMORY
- Publication number 20140334222
- Publication date Nov 13, 2014
- UNITY SEMICONDUCTOR CORPORATION
- Bruce Lynn Bateman
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Element With a Reactive Metal Layer
- Publication number 20140211542
- Publication date Jul 31, 2014
- UNITY SEMICONDUCTOR CORPORATION
- Christophe J. Chevallier
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE FABRICATION
- Publication number 20130059436
- Publication date Mar 7, 2013
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...
- Publication number 20120307542
- Publication date Dec 6, 2012
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Application
CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-PO...
- Publication number 20120292585
- Publication date Nov 22, 2012
- UNITY SEMICONDUCTOR CORPORATION
- Robin Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Two Terminal Re Writeable Non Volatile Ion Transport Memory Device
- Publication number 20120087174
- Publication date Apr 12, 2012
- UNITY SEMICONDUCTOR CORPORATION
- DARRELL RINERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Read Current Architecture For Memory
- Publication number 20120075914
- Publication date Mar 29, 2012
- UNITY SEMICONDUCTOR CORPORATION
- BRUCE BATEMAN
- G11 - INFORMATION STORAGE
Information Patent Application
Method For Fabricating Multi Resistive State Memory Devices
- Publication number 20120064691
- Publication date Mar 15, 2012
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Element With A Reactive Metal Layer
- Publication number 20120033481
- Publication date Feb 9, 2012
- UNITY SEMICONDUCTOR CORPORATION
- DARRELL RINERSON
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device Using A Dual Layer Conductive Metal Oxide Structure
- Publication number 20110315943
- Publication date Dec 29, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- F01 - MACHINES OR ENGINES IN GENERAL ENGINE PLANTS IN GENERAL STEAM ENGINES
Information Patent Application
Memory Device Using Ion Implant Isolated Conductive Metal Oxide
- Publication number 20110315948
- Publication date Dec 29, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- F01 - MACHINES OR ENGINES IN GENERAL ENGINE PLANTS IN GENERAL STEAM ENGINES
Information Patent Application
Threshold Device For A Memory Array
- Publication number 20110291067
- Publication date Dec 1, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Julie Casperson Brewer
- G11 - INFORMATION STORAGE
Information Patent Application
TRI LAYER METAL OXIDE REWRITABLE NON VOLATILE TWO TERMINAL MEMORY E...
- Publication number 20110278532
- Publication date Nov 17, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE
Information Patent Application
Local bit lines and methods of selecting the same to access memory...
- Publication number 20110188281
- Publication date Aug 4, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Chang Hua Siau
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-resistive state memory device with conductive oxide electrodes
- Publication number 20110186803
- Publication date Aug 4, 2011
- UNITY SEMICONDUCTOR CORPORATION
- Darrell Rinerson
- G11 - INFORMATION STORAGE

Darrell Rinerson

Person

Patents Grantslast 30 patents

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Local bit lines and methods of selecting the same to access memory...

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

Local bit lines and methods of selecting the same to access memory...

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

Local bit lines and methods of selecting the same to access memory...

Low read current architecture for memory

Two-terminal reversibly switchable memory device

Memory element with a reactive metal layer

Memory element with a reactive metal layer

Low read current architecture for memory

Memory element with a reactive metal layer

Two-terminal reversibly switchable memory device

Local bit lines and methods of selecting the same to access memory...

Low read current architecture for memory

Memory element with a reactive metal layer

Method for fabricating multi-resistive state memory devices

Device fabrication

Threshold device for a memory array

Device fabrication

Local bit lines and methods of selecting the same to access memory...

Memory device using ion implant isolated conductive metal oxide

Continuous plane of thin-film materials for a two-terminal cross-po...

Method for fabricating multi-resistive state memory devices

Low read current architecture for memory

Patents Applicationslast 30 patents

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

LOW READ CURRENT ARCHITECTURE FOR MEMORY

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE

LOW READ CURRENT ARCHITECTURE FOR MEMORY

Memory Element With a Reactive Metal Layer

DEVICE FABRICATION

LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCE...

CONTINUOUS PLANE OF THIN-FILM MATERIALS FOR A TWO-TERMINAL CROSS-PO...

Two Terminal Re Writeable Non Volatile Ion Transport Memory Device

Low Read Current Architecture For Memory

Method For Fabricating Multi Resistive State Memory Devices

Memory Element With A Reactive Metal Layer

Memory Device Using A Dual Layer Conductive Metal Oxide Structure

Memory Device Using Ion Implant Isolated Conductive Metal Oxide

Threshold Device For A Memory Array

TRI LAYER METAL OXIDE REWRITABLE NON VOLATILE TWO TERMINAL MEMORY E...

Local bit lines and methods of selecting the same to access memory...

Multi-resistive state memory device with conductive oxide electrodes