Two-terminal reversibly switchable memory device

Information

  • Patent Grant
  • 11672189
  • Patent Number
    11,672,189
  • Date Filed
    Monday, March 8, 2021
    3 years ago
  • Date Issued
    Tuesday, June 6, 2023
    a year ago
Abstract
A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
Description
BACKGROUND OF THE INVENTION
Field of the Intention

The present invention relates to computer memory and more specifically to non-volatile memory.


Description of the Related Art

Memory can either be classified as volatile or nonvolatile. Volatile memory is memory that loses its contents when the power is turned off. In contrast, non-volatile memory does not require a continuous power supply to retain information. Most non-volatile memories use solid-state memory devices as memory elements.


Since the 1960s, a large body of literature has evolved that describes switching and memory effects in metal-insulator-metal structures with thin insulators. One of the seminal works was “New Conduction and Reversible Memory Phenomena in Thin Insulating Films” by J. G. Simmons and R. R. Verderber in 301 Proc. Roy. Soc. 77-102 (1967), incorporated herein by reference for all purposes. Although the mechanisms described by Simmons and Vederber have since been cast into doubt, their contribution to the field is great.


However, nobody has successfully implemented a metal-insulator-metal structure into a commercial solid-state memory device. In the text “Oxides and Oxide Films,” volume 6, edited by A. K. Vijh (Marcel Drekker 1981) 251-325, incorporated herein by reference for all purposes, chapter 4, written by David P. Oxley, is entirely devoted to “Memory Effects in Oxide Films.” In that text, Oxley says “It is perhaps saddening to have to record that, even after 10 years of effort, the number of applications for these oxide switches is so limited.” He goes on to describe a “need for caution before any application is envisaged. This caution can only be exercised when the physics of the switching action is understood; this, in turn, must await a full knowledge of the transport mechanisms operating in any switch for which a commercial use is envisaged.”


In 2002, over twenty years after writing that chapter, Oxley revisited the subject in “The Electroformed metal-insulator-metal structure: A comprehensive model” by R. E. Thurstans and D. P. Oxley 35 J. Phys. D. Appl. Phys. 802-809, incorporated herein by reference for all purposes. In that article, the authors describe a model that identifies the conduction process as “trap-controlled and thermally activated tunneling between metal islands produced in the forming process.” “Forming” (or “electroforming”) is described as “the localized filamentary movement of metallic anode material through the dielectric, induced by the electric field. Here it is important to note that the evaporated dielectric may contain voids and departures from stoichiometry. When resulting filaments through the dielectric carry sufficient current, they rupture to leave a metal island structure embedded in the dielectric. Electronic conduction is possible through this structure by activating tunneling.”


However, the authors caution, “The forming process is complex and inherently variable. Also tunneling barriers are susceptible to changes in their characteristics when exposed to water vapour, organic species and oxygen . . . . Thus, device characteristics can never be expected to be produced consistently or be stable over long periods without passivation, effective encapsulation and a better understanding of the dynamics of the forming process.”


In seemingly unrelated research, certain conductive metal oxides (CMOs), have been identified as exhibiting a memory effect after being exposed to an electronic pulse. U.S. Pat. No. 6,204,139, issued Mar. 20, 2001 to Liu et al., incorporated herein by reference for all purposes, describes some perovskite materials that exhibit memory characteristics. The perovskite materials are also described by the same researchers in “Electric-pulse-induced reversible resistance change effect in magnetoresistive films,” Applied Physics Letters, Vol. 76, No. 19, 8 May 2000, and “A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films,” in materials for the 2001 Non-Volatile Memory Technology Symposium, all of which are hereby incorporated by reference for all purposes.


In U.S. Pat. No. 6,531,371 entitled “Electrically programmable resistance cross point memory” by Hsu et al, incorporated herein by reference for all purposes, resistive cross point memory devices are disclosed along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes.


Similarly, the IBM Zurich Research Center has also published three technical papers that discuss the use of metal oxide material for memory applications: “Reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters, Vol. 77, No. 1, 3 Jul. 2000, “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTi03 single crystals,” Applied Physics Letters, Vol. 78, No. 23, 4 Jun. 2001, and “Electric current distribution across a metal-insulator-metal structure during bistable switching, “Journal of Applied Physics, Vol. 90, No. 6, 15 Sep. 2001, all of which are hereby incorporated by reference for all purposes.


There are continuing efforts to incorporate solid state memory devices into a commercial non-volatile RAM.





BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which:



FIG. 1A depicts a perspective view of an exemplary cross point memory array employing a single layer of memory;



FIG. 1B depicts a perspective view of an exemplary stacked cross point memory array employing four layers of memory;



FIG. 2A depicts a plan view of selection of a memory cell in the cross point array depicted in FIG. 1A;



FIG. 2B depicts a perspective view of the boundaries of the selected memory cell depicted in FIG. 2A;



FIG. 3 depicts a generalized cross-sectional representation of a memory cell that can be used in a transistor memory array;



FIG. 4A depicts a block diagram of a representative implementation of an exemplary 1 MB memory;



FIG. 4B depicts a block diagram of an exemplary memory that includes sensing circuits that are capable of reading multiple bits;



FIG. 5A depicts a block diagram representing the basic components of one embodiment of a memory element;



FIG. 5B depicts a block diagram of the memory elements of FIG. 5A in a two-terminal memory cell;



FIG. 5C depicts a block diagram of the memory element of FIG. 5A in a three-terminal memory cell;



FIG. 6A depicts a block diagram of the memory cell of FIG. 5B where oxygen movement results in a low conductivity oxide;



FIG. 6B depicts a block diagram of a two-terminal memory cell of FIG. 5B where a low conductivity oxide is self-limiting;



FIG. 7 depicts a block diagram of a two-terminal memory cell using another memory element embodiment;



FIG. 8A depicts a block diagram of the memory cell of FIG. 7 where a low conductivity region is created in a mixed valence oxide; and



FIG. 8B depicts a block diagram of the memory cell of FIG. 8A that includes an oxygen repository.





It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the depictions in the FIGs. are not necessarily to scale.


DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the present invention.


The Memory Array


Conventional nonvolatile memory requires three terminal MOSFET-based devices. The layout of such devices is not ideal, usually requiring an area of at least 8f2 for each memory cell, where f is the minimum feature size. However, not all memory elements require three terminals. If, for example, a memory element is capable of changing its electrical properties (e.g., resistivity) in response to a voltage pulse, only two terminals are required. With only two terminals, a cross point array layout that allows a single cell to be fabricated to a size of 4f2 can be utilized.



FIG. 1A depicts a perspective view of an exemplary cross point memory array 100 employing a single layer of memory. A bottom layer of x-direction conductive array lines 105 is orthogonal to a top layer of y-direction conductive array lines 110. The x-direction conductive array lines 105 act as a first terminal and they direction conductive array lines 110 act as a second terminal to a plurality of memory plugs 115, which are located at the intersections of the conductive array lines 105 and 110. The conductive array lines 105 and 110 are used to both deliver a voltage pulse to the memory plugs 115 and carry current through the memory plugs 115 in order to determine their resistive states.


Conductive array line layers 105 and 110 can generally be constructed of any conductive material, such as aluminum, copper, tungsten or certain ceramics. Depending upon the material, a conductive array line would typically cross between 64 and 8192 perpendicular conductive array lines. Fabrication techniques, feature size and resistivity of material may allow for shorter or longer lines. Although the x-direction and y-direction conductive array lines can be of equal lengths (forming a square cross point array) they can also be of unequal lengths (forming a rectangular cross point array), which may be useful if they are made from different materials with different resistivities.



FIG. 2A illustrates selection of a memory cell 205 in the cross point array 100. The point of intersection between a single x-direction conductive array line 210 and a single y-direction conductive array line 215 uniquely identifies the single memory cell 205. FIG. 2B illustrates the boundaries of the selected memory cell 205. The memory cell is a repeatable unit that can be theoretically extended in one, two or even three dimensions. One method of repeating the memory cells in the z-direction (orthogonal to the x-y plane) is to use both the bottom and top surfaces of conductive array lines 105 and 110, creating a stacked cross point array.



FIG. 1B depicts an exemplary stacked cross point array 150 employing four memory layers 155, 160, 165, and 170. The memory layers are sandwiched between alternating layers of x-direction conductive array lines 175, 180 and 185 and y-direction conductive array lines 190 and 195 such that each memory layer 155, 160, 165, and 170 is associated with only one x-direction conductive array line layer and one y-direction conductive array line layer. Although the top conductive array line layer 185 and bottom conductive array line layer 175 are only used to supply voltage to a single memory layer 155 and 170, the other conductive array line layers 180, 190, and 195 can be used to supply voltage to both a top and a bottom memory layer 155, 160, 165, or 170.


Referring back to FIG. 2B, the repeatable cell that makes up the cross point array 100 can be considered to be a memory plug 255, plus ½ of the space around the memory plug, plus ½ of an x-direction conductive array line 210 and ½ of a y-direction conductive array line 215. Of course, ½ of a conductive array line is merely a theoretical construct, since a conductive array line would generally be fabricated to the same width, regardless of whether one or both surfaces of the conductive array line was used. Accordingly, the very top and very bottom layers of conductive array lines (which use only one surface) would typically be fabricated to the same size as all other layers of conductive array lines.


One benefit of the cross point array is that the active circuitry that drives the cross point array 100 or 150 can be placed beneath the cross point array, therefore reducing the footprint required on a semiconductor substrate. However, the cross point array is not the only type of memory array that can be used with a two-terminal memory element. For example, a two-dimensional transistor memory array can incorporate a two-terminal memory element. While the memory element in such an array would be a two-terminal device, the entire memory cell would be a three-terminal device.



FIG. 3 is a generalized diagrammatic representation of a memory cell 300 that can be used in a transistor memory array. Each memory cell 300 includes a transistor 305 and a memory plug 310. The transistor 305 is used to permit current from the data line 315 to access the memory plug 310 when an appropriate voltage is applied to the select line 320, which is also the transistor's gate. The reference line 325 might span two cells if the adjacent cells are laid out as the mirror images of each other.


Memory Chip Configuration



FIG. 4A is a block diagram of a representative implementation of an exemplary 1 MB memory 400A. Physical layouts might differ, but each memory bit block 405 can be formed on a separate portion of a semiconductor substrate. Input signals into the memory 400A can include an address bus 430, a control bus 440, some power supplies 450 (typically Vcc and ground—the other signals of bus 450 can be internally generated by the 1 MB memory 400A), and a data bus 460. The control bus 440 typically includes signals to select the chip, to signal whether a read or write operation should be performed, and to enable the output buffers when the chip is in read mode. The address bus 430 specifies which location in the memory array is accessed—some addresses going to the X block 470 (typically including a predecoder and an X-decoder) to select one line out of the horizontal array lines. The other addresses go to a Y block 480 (typically including a predecoder and a Y-decoder) to apply the appropriate voltage on specific vertical lines. Each memory bit block 405 operates on one line of the memory chip data bus 460.


The reading of data from a memory array 420 is relatively straightforward: an x-line is energized, and current is sensed by the sensing circuits 410 on the energized y-lines and converted to bits of information.



FIG. 4B is a block diagram of an exemplary memory 400B that includes sensing circuits 415 that are capable of reading multiple bits. The simultaneous reading of multiple bits involves sensing current from multiple y-lines simultaneous.


During a write operation, the data is applied from the data bus 460 to the input buffers and data drivers 490 to the selected vertical lines, or bit lines. Specifically, when binary information is sent to the memory chip 400B, it is typically stored in latch circuits within the circuits 495. Within the circuits 495, each y-line can either have an associated driver circuit or a group of y-lines can share a single driver circuit if the non-selected lines in the group do not cause the unselected memory plugs to experience any change in resistance, typically by holding the non-selected lines to a constant voltage. As an example, there may be 1024 y-lines in a cross point array, and the page register may include 8 latches, in which case they-block would decode 1 out of 128 y-lines and connect the selected lines to block 495. The driver circuit then writes the 1 or 0 to the appropriate memory plug. The writing can be performed in multiple cycles. In a scheme described in PCT Patent Application No. PCT/US04/13836, filed May 3, 2004, incorporated herein by reference, all the is can be written during a first cycle and all the 0s can be written during a second cycle. As described below, certain memory plugs can have multiple stable distinct resistive states. With such multi-level resistance memory plugs, driver circuits could program, for example, states of 00, 01, 10 or 11 by varying write voltage magnitude or pulse length.


It is to be noted that such an architecture can be expanded to create a memory where one array handles all the bits of the data bus, as opposed to having multiple arrays, or memory bit blocks as described above. For example, if the data bus, or memory data organization, also called data width, is 16-bit wide, the y-block of one cross point array can be made to decode 16 lines simultaneously. By applying the techniques of simultaneous reads and 2-cycle writes, such a memory chip with only one array can read and program 16-bit words.


Memory Plug


Each memory plug contains layers of materials that may be desirable for fabrication or functionality. For example, a non-ohmic characteristic that exhibit a very high resistance regime for a certain range of voltages (VNO− to VNO+) and a very low resistance regime for voltages above and below that range might be desirable. In a cross point array, a non-ohmic characteristic could prevent leakage during reads and writes if half of both voltages were within the range of voltages VNO− to VNO+. If each conductive array line carried ½ Vw, the current path would be the memory plug at the intersection of the two conductive array lines that each carried ½ Vw. The other memory plugs would exhibit such high resistances from the non-ohmic characteristic that current would not flow through the half-selected plugs.


A non-ohmic device might be used to cause the memory plug to exhibit a non-linear resistive characteristic. Exemplary non-ohmic devices include three-film metal-insulator-metal (MIM) structures and back-to-back diodes in series. Separate non-ohmic devices, however, may not be necessary. Certain fabrications of the memory plug can cause a non-ohmic characteristic to be imparted to the memory cell. While a non-ohmic characteristic might be desirable in certain arrays, it may not be required in other arrays.


Electrodes will typically be desirable components of the memory plugs, a pair of electrodes sandwiching the memory element. If the only purpose of the electrodes is as a barrier to prevent metal inter-diffusion, then a thin layer of non-reactive metal, e.g. TiN, TaN, Pt, Au, and certain metal oxides could be used. However, electrodes may provide advantages beyond simply acting as a metal inter-diffusion barrier. Electrodes (formed either with a single layer or multiple layers) can perform various functions, including to: prevent the diffusion of metals, oxygen, hydrogen and water; act as a seed layer in order to form a good lattice match with other layers; act as adhesion layers; reduce stress caused by uneven coefficients of thermal expansion; and provide other benefits. Additionally, the choice of electrode layers can affect the memory effect properties of the memory plug and become part of the memory element.


The “memory element electrodes” are the electrodes (or, in certain circumstances, the portion of the conductive array lines) that the memory elements are sandwiched in-between. As used herein, memory element electrodes are what allow other components to be electrically connected to the memory element. It should be noted that both cross point arrays and transistor memory arrays have exactly two memory element electrodes since the memory plug has exactly two terminals, regardless of how many terminals the memory cell has. Those skilled in the art will appreciate that a floating gate transistor, if used as a memory element, would have exactly three memory element electrodes (source, drain and gate).


Memory Effect


The memory effect is a hysteresis that exhibits a resistive state change upon application of a voltage while allowing non-destructive reads. A nondestructive read means that the read operation has no effect on the resistive state of the memory element. Measuring the resistance of a memory cell is generally accomplished by detecting either current after the memory cell is held to a known voltage, or voltage after a known current flows through the memory cell. Therefore, a memory cell that is placed in a high resistive state R0 upon application of −Vw and a low resistive state R1 upon application of +Vw should be unaffected by a read operation performed at −VR or +VR. In such materials a write operation is not necessary after a read operation. It should be appreciated that the magnitude of |−VR| does not necessarily equal the magnitude of |+VR|.


Furthermore, it is possible to have a memory cell that can be switched between resistive states with voltages of the same polarity. For example, in the paper “The Electroformed metal-insulator-metal structure: a comprehensive model,” already incorporated by reference, Thurstans and Oxley describe a memory that maintains a low resistive state until a certain VP is reached. After VP is reached the resistive state can be increased with voltages. After programming, the high resistive state is then maintained until a VT is reached. The VT is sensitive to speed at which the program voltage is removed from the memory cell. In such a system, programming R1 would be accomplished with a voltage pulse of VP, programming R0 would be accomplished with a voltage pulse greater than VP, and reads would occur with a voltages below VT. Intermediate resistive states (for multi-level memory cells) are also possible.


The R1 state of the memory plug may have a best value of 10 kΩ to 100Ω. If the R1 state resistance is much less than 10 kΩ, the current consumption will be increased because the cell current is high, and the parasitic resistances will have a larger effect. If the R1 state value is much above 100Ω, the RC delays will increase access time. However, workable single state resistive values may also be achieved with resistances from 5 kΩ to lMΩ and beyond with appropriate architectural improvements. Typically, a single state memory would have the operational resistances of R0 and R1 separated by a factor of 10.


Since memory plugs can be placed into several different resistive states, multi-bit resistive memory cells are possible. Changes in the resistive property of the memory plugs that are greater than a factor of 10 might be desirable in multi-bit resistive memory cells. For example, the memory plug might have a high resistive state of R00, a medium-high resistive state of R01, a medium-low resistive state of R10 and a low resistive state of R11. Since multi-bit memories typically have access times longer than single-bit memories, using a factor greater than a 10 times change in resistance from R11 to R00 is one way to make a multi-bit memory as fast as a single-bit memory. For example, a memory cell that is capable of storing two bits might have the low resistive state be separated from the high resistive state by a factor of 100. A memory cell that is capable of storing three or four bits of information might require the low resistive state be separated from the high resistive state by a factor of 1000.


Creating the Memory Effect with Tunneling


Tunneling is a process whereby electrons pass through a barrier in the presence of an electric filed. Tunneling is exponentially dependent on a barrier's width and the square root of its height. Barrier height is typically defined as the potential difference between the Fermi energy of a first conducting material and the band edge of a second insulating material. The Fermi energy is that energy at which the probability of occupation of an electron state is 50%. Barrier width is the physical thickness of the insulating material.


The barrier height might be modified if carriers or ions are introduced into the second material, creating an additional electric field. A barrier's width can be changed if the barrier physically changes shape, either growing or shrinking. In the presence of a high electric field, both mechanisms could result in a change in conductivity.


Although the following discussion focuses mainly on purposefully modifying the barrier width, those skilled in the art will appreciate that other mechanisms can be present, including but not limited to: barrier height modification, carrier charge trapping space-charge limited currents, thermionic emission limited conduction, and/or electrothermal Poole-Frenkel emission.



FIG. 5A is a block diagram representing the basic components of one embodiment of a memory element 500, FIG. 5B is a block diagram of the memory element 500 in a two-terminal memory cell, and FIG. 5C is a block diagram of the memory element embodiment of FIG. 5A in a three-terminal memory cell.



FIG. 5A shows an electrolytic tunnel barrier 505 and an ion reservoir 510, two basic components of the memory element 500. FIG. 5B shows the memory element 500 between a top memory electrode 515 and a bottom memory electrode 520. The orientation of the memory element (i.e., whether the electrolytic tunnel barrier 505 is near the top memory electrode 515 or the bottom memory electrode 520) may be important for processing considerations, including the necessity of seed layers and how the tunnel barrier reacts with the ion reservoir 510 during deposition. FIG. 5C shows the memory element 500 oriented with the electrolytic tunnel barrier 505 on the bottom in a three-terminal transistor device, having a source memory element electrode 525, gate memory element electrode 530 and a drain memory element electrode 535. In such an orientation, the electrolytic tunnel barrier 505 could also function as a gate oxide.


Referring back to FIG. 5A, the electrolytic tunnel barrier 505 will typically be between 10 and less than 50 angstroms. If the electrolytic tunnel barrier 505 is much greater than 50 angstroms, then the voltage that is required to create the electric field necessary to move electrons through the memory element 500 via tunneling becomes too high for most electronic devices. Depending on the electrolytic tunnel barrier 505 material, a preferred electrolytic tunnel barrier 505 width might be between 15 and 40 angstroms for circuits where rapid access times (on the order of tens of nanoseconds, typically below 100 ns) in small dimension devices (on the order of hundreds of nanometers) are desired.


Fundamentally, the electrolytic tunnel barrier 505 is an electronic insulator and an ionic electrolyte. As used herein, an electrolyte is any medium that provides an ion transport mechanism between positive and negative electrodes. Materials suitable for some embodiments include various metal oxides such as Al203, Ta205, Hf02 and Zr02. Some oxides, such as zirconia might be partially or fully stabilized with other oxides, such as CaO, MgO, or Y2O3, or doped with materials such as scandium.


The electrolytic tunnel barrier 505 will typically be of very high quality, being as uniform as possible to allow for predictability in the voltage required to obtain a current through the memory element 500. Although atomic layer deposition and plasma oxidation are examples of methods that can be used to create very high quality tunnel barriers, the parameters of a particular system will dictate its fabrication options. Although tunnel barriers can be obtained by allowing a reactive metal to simply come in contact with an ion reservoir 510, as described in PCT Patent Application No. PCT/US04/13836, filed May 3, 2004, already incorporated herein by reference, such barriers may be lacking in uniformity, which may be important in some embodiments. Accordingly, in a preferred embodiment of the invention the tunnel barrier does not significantly react with the ion reservoir 510 during fabrication.


With standard designs, the electric field at the tunnel barrier 505 is typically high enough to promote tunneling at thicknesses between 10 and 50 angstroms. The electric field is typically higher than at other points in the memory element 500 because of the relatively high serial electronic resistance of the electrolytic tunnel barrier 505. The high electric field of the electrolytic tunnel barrier 505 also penetrates into the ion reservoir 510 at least one Debye length. The Debye length can be defined as the distance which a local electric field affects distribution of free charge carriers. At an appropriate polarity, the electric field within the ion reservoir 510 causes ions (which can be positively or negatively charged) to move from the ion reservoir 510 through the electrolytic tunnel barrier 505, which is an ionic electrolyte.


The ion reservoir 510 is a material that is conductive enough to allow current to flow and has mobile ions. The ion reservoir 510 can be, for example, an oxygen reservoir with mobile oxygen ions. Oxygen ions are negative in charge, and will flow in the direction opposite of current.



FIG. 6A is a block diagram where a redox reaction between the oxygen reservoir 635 and a complementary reservoir 615 results in a low conductivity oxide 640 and an oxygen-depleted low conductivity region 620. In the case where the ion reservoir 510 is made up of negative oxygen ions, an appropriate complementary reservoir 615 would be positively charged ions. Additionally, the complementary reservoir 615 for the embodiment depicted in FIG. 6A should be conductive in its non-oxidized state and exhibit low conductivity in its oxidized state. Accordingly, many conductive metals (including alkali metals, alkaline earth metals, transition metals and other metals) could act as a complementary reservoir 615. For ease of fabrication, the complimentary reservoir 615 may be the non-oxidized form of the same material that is used for the electrolytic tunnel barrier 505.


When an electric field is applied across the electrolytic tunnel barrier 505, the electric field would penetrate at least one Debye length into the oxygen reservoir 635. The negatively charged oxygen ions migrate through the electrolytic tunnel barrier 505 to combine with positively charged metal ions in the complementary reservoir 615, creating a low conductivity oxide 640. This low conductivity oxide 640 is cumulative with the electrolytic tunnel barrier 505, forcing electrons to tunnel a greater distance to reach the conductive complimentary reservoir 615. Because of the exponential effect of barrier width on tunneling, the low conductivity oxide 640 can be just a few angstroms wide and still have a very noticeable effect on the memory element's effective resistance.


Those skilled in the art will appreciate that redox reaction can occur at either the top or bottom surface of the electrolytic tunnel barrier 505. The low conductivity oxide 640 will form at the top of the electrolytic tunnel barrier 505 if the mobility of the complementary ions is greater than the mobility of the oxygen ions through the electrolytic tunnel barrier 505. Conversely, if the mobility of oxygen ions is greater than the mobility of the complementary ions through the electrolytic tunnel barrier 505, then the low conductivity oxide 640 will form at the bottom of the electrolytic tunnel barrier 505.


The stability of metal oxides will depend on its activation energy. Reversing the redox reaction for many metal oxides, such as Hf and Al, requires a great amount of energy, making such high activation energy cells convenient for use as one-time programmable memories. Oxides with low activation energy, such as RuOX and CuOX, are usually desirable for reprogrammable memories.


One optimization would be to use the polarity that is less sensitive to read disturbs during reads. For write once memory this may be complementary to the write polarity. Alternatively, alternating read polarities can be used. Another optimization for certain embodiments could be to limit the size of the complementary reservoir 615.



FIG. 6B is a block diagram where the complimentary reservoir 615 is fabricated to be self-limiting. Since only a small amount of the complementary reservoir 615 is deposited, the amount of positive ions available to combine with the free oxygen ions is limited. Once all the free ions in the complimentary reservoir 615 are consumed, no more low conductivity oxide 640 could be formed.


In most cases the effective width of the tunneling barrier is limited only by the availability of ions in the reservoirs 615 and 635. Since many different barrier widths can be formed multiple bits per cell can be easily implemented with different resistive states.


Referring back to FIG. 5A, certain ion reservoirs 510 have the physical property of being less conductive in an oxygen-deficient state. Some examples of materials that have mobile oxygen ions and are less conductive in an oxygen-deficient state include certain perovskites (a perovskite generally being in the form of an ABX3 structure, where A has an atomic size of 1.0-1.4 Å and B has an atomic size of 0.45-0.75 Å for the case where X is either oxygen or fluorine) such as SrRuO3 (SRO), Pr0.7Ca0.3MnO3, Pr0.5Ca0.5MnO3 and other PCMOs. Many of these ion reservoirs 510 are potentially mixed valence oxides. For example, PCMO might be more conductive when its manganese ion is in its Mn3+ state, but less conductive when its manganese ion is in its Mn4+ state.


Accordingly, as shown in FIG. 6A, certain oxygen reservoirs 635 will additionally form an oxygen-depleted low conductivity region 620 that also adds to the memory effect. Those skilled in the art will appreciate that either the oxygen-depleted low conductivity region 620 or the low conductivity oxide 640 may independently be sufficient to create an acceptable memory effect or, if the conduction mechanisms are different (e.g., small polaron hopping through the oxygen-depleted low conductivity region 620 and tunneling through the low conductivity oxide 640) one mechanism may even dominate the overall conduction through the memory element 500. Accordingly, memory cells can be designed to take advantage of only one phenomenon or the other or both.


Creating the Memory Effect with Oxygen Depletion



FIG. 7 is a block diagram representing another embodiment of a memory element 700 in a two-terminal memory cell where an oxygen-depleted low conductivity region in an otherwise conductive material creates the majority of the memory effect. FIG. 7 shows a mixed valence oxide 710 and a mixed electronic ionic conductor 705, two basic components of the memory element 700 between a top memory electrode 515 and a bottom memory electrode 520. As with the embodiment of FIG. 5A, the orientation of the memory element may be important for processing considerations. It should be appreciated that the memory element can also be used in a three-terminal memory cell, similar to what is depicted in FIG. 5C.


In these embodiments, ion deficiency (which, in the embodiment of FIG. 7, is oxygen) will cause an otherwise conductive material to become less conductive. The mixed valence oxide 710 will generally be crystalline, either as a single crystalline structure or a polycrystalline structure. In one specific embodiment the crystalline structure maintains its basic crystallinity (with some degree of deformation) in both valence states. By maintaining its crystallinity, both the physical stresses on the memory element may be reduced and the reversibility of the process may be easier to achieve.


The mixed electronic ionic conductor 705 is similar, and in some cases identical, to the electrolytic tunnel barrier 505 of FIGS. 6A and 6B. Like the electrolytic tunnel barrier 505, the mixed electronic ionic conductor 705 is both an electrolyte and creates a high electric field that promotes ionic movement. However, whether the mixed electronic ionic conductor 705 promotes actual tunneling is not critical.


In FIG. 8A the mixed electronic ionic conductor 705 also acts as an oxygen repository, temporarily holding oxygen until an opposite polarity voltage pulse pushes the oxygen back into the mixed valence oxide 710. In FIG. 8B a separate oxygen repository 715 layer is used to hold the oxygen. The oxygen repository 715 may be identical to the previously described complementary reservoir 615 or even certain types of oxygen reservoirs 635 such as IrOX. If a redox reaction creates an oxide in the oxygen repository 715, the activation energy required to disassociate the oxygen from the oxide will influence whether the memory is used as a one time programmable memory or a rewritable memory.


In one specific embodiment that is similar to an inverted embodiment of what is shown in FIG. 8A, the bottom electrode 520 might be a 500 Angstrom layer of platinum, DC magnetron sputtered with 180 watts applied to a platinum target in 4 mTorr of argon at 450° C. and then cooled in-situ for at least 10 minutes in the sputter ambient gas environment of 4 mTorr of argon.


The mixed valence oxide 710 might be a 500 Angstrom layer of a PCMO perovskite, RF magnetron sputtered in 10 mTorr of argon at 550° C. by applying 120 watts to a Pr0.7Ca0.3MnO3 target (made with hot isostatic pressing or HIP), afterwards cooled in-situ for 10 minutes in the sputter ambient gas environment of 10 mTorr of argon, then cooled for another 10 minutes in a load lock chamber at 600 Torr of oxygen.


The mixed electronic ionic conductor 705 might be 20 or 30 Angstroms of some type of AlOX, RF magnetron sputtered in 4 mTorr of argon with 1% oxygen at 300° C. by applying 150 watts to an Al2O3 target (also made with HIP), and then annealed for 30 minutes at 250° C. in the sputter ambient gas environment of 4 mTorr of argon with 1% O2.


If an embodiment similar to FIG. 8B were desired, an oxygen repository 715 of 200 Angstroms of aluminum metal could be DC magnetron sputtered with 250 watts applied to an aluminum target in 4 mTorr of argon at 25° C.


The top electrode 515 might be 500 Angstroms of platinum, DC magnetron sputtered with 180 watts applied to a platinum target in 4 mTorr of argon at 25° C.


CONCLUDING REMARKS

Although the invention has been described in its presently contemplated best mode, it is clear that it is susceptible to numerous modifications, modes of operation and embodiments, all within the ability and skill of those familiar with the art and without exercise of further inventive activity. For example, although the ion reservoir was described as being negative in connection with the oxygen reservoir, a positively charged ion reservoir may have the same functionality, as long as the other physical requirements of the specific embodiments are met. Furthermore, while the theories provided above are one possible explanation of how the various materials interact, the inventors do not wish to be bound by any theoretical explanation. Accordingly, that which is intended to be protected by Letters Patent is set forth in the claims and includes all variations and modifications that fall within the spirit and scope of the claims.

Claims
  • 1. A memory element, comprising: an oxygen repository;a mixed valence conductive oxide that is less conductive in its oxygen deficient state; andan electrolytic tunnel barrier that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
  • 2. The memory element of claim 1, wherein the mixed valence conductive oxide has a substantially crystalline structure.
  • 3. The memory element of claim 2, wherein the mixed valence conductive oxide is placed in its oxygen deficient state during normal operation and retains its substantially crystalline structure during the normal operation.
  • 4. The memory element of claim 1, wherein a conductivity of the memory element is indicative of a memory state and the memory state is determined non-destructively.
  • 5. The memory element of claim 1, wherein the electric field causes oxygen from the mixed valence conductive oxide to move into the electrolytic tunnel barrier during normal operation.
  • 6. The memory element of claim 5, wherein the electric field causes oxygen from the mixed valence conductive oxide to move through the electrolytic tunnel barrier during normal operation.
  • 7. The memory element of claim 1, wherein the memory element Is part of a memory cell having a feature size of not more than about 4f2, f being the minimum fabrication line width.
  • 8. A memory element, comprising: an oxygen repository;an electrolytic tunneling barrier having a tunnel barrier width; anda conductive material having a low conductivity region that forms an effective tunnel barrier width greater than the tunnel barrier width, the low conductivity region being formed responsive to a voltage across the memory element.
  • 9. The memory element of claim 8, wherein a conductivity of the memory element is indicative of a memory state and the memory state is determined non-destructively.
  • 10. The memory element of claim 8, wherein an electric field causes anion motion from the conductive material into the electrolytic tunneling barrier during normal operation.
  • 11. The memory element of claim 10, Wherein the electric field causes anion motion from the conductive material through the electrolytic tunneling barrier during normal operation.
  • 12. The memory element of claim 8, wherein the conductive material has a substantially crystalline structure.
  • 13. The memory element of claim 12, wherein the conductive material retains its substantially crystalline structure during normal operation.
  • 14. The memory element Of claim 8, wherein the memory element is part of a memory cell having a feature size of not more than about 4f2, f being the minimum fabrication line width.
  • 15. A two terminal electrical device, comprising: an oxygen repository;a tunneling barrier having a tunnel barrier width of less than approximately 50 angstroms; anda conductive material in series with the tunneling barrier and having mobile ions;wherein the tunneling barrier is an electrolyte to the mobile ions of the conductive material; andwherein the tunneling barrier has a first conductivity at a read voltage and a second conductivity at the read voltage after being applied a programming voltage.
  • 16. The two terminal electrical device of claim 15, wherein the conductivity of the electrical device is indicative of a memory state and the memory state is determined non-destructively.
  • 17. The two terminal electrical device of claim 15, wherein an electric field causes anion motion from the conductive material into the tunneling barrier during normal operation.
  • 18. The two terminal electrical device of claim 17, wherein the electric field causes anion motion from the conductive material through the tunneling barrier during normal operation.
  • 19. The two terminal electrical device of claim 15, wherein the conductive material has a substantially crystalline structure.
  • 20. The two terminal electrical device of claim 19, wherein the conductive material retains its substantially crystalline structure during normal operation.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/864,051, filed on Apr. 30, 2020, which is a continuation of U.S. patent application Ser. No. 16/262,841, filed on Jan. 30, 2019, now U.S. Pat. No. 10,680,171, which is a continuation of U.S. patent application Ser. No. 15/797,452, filed on Oct. 30, 2017, now U.S. Pat. No. 10,224,480, which is a continuation of U.S. patent application Ser. No. 14/844,805, filed on Sep. 3, 2015, now U.S. Pat. No. 9,831,425, which is a continuation of U.S. patent application Ser. No. 14/463,518, filed on Aug. 19, 2014, now U.S. Pat. No. 9,159,913, which is a continuation of U.S. patent application Ser. No. 12/456,627, filed on Jun. 18, 2009, now abandoned, which is a continuation of U.S. patent application Ser. No. 11/095,026, filed on Mar. 30, 2005, now abandoned, which is a continuation-in-part of U.S. patent application Ser. No. 10/934,951, filed on Sep. 3, 2004, now U.S. Pat. No. 7,538,338, and which is a continuation-in-part of U.S. patent application Ser. No. 10/773,549, filed on Feb. 6, 2004, now U.S. Pat. No. 7,082,052, all of which are hereby incorporated by reference herein in their entirety for all purposes.

US Referenced Citations (243)
Number Name Date Kind
3886577 Buckley May 1975 A
4843059 Deslandes et al. Jun 1989 A
5296716 Ovshinksy et al. Mar 1994 A
5479317 Ramesh Dec 1995 A
5483482 Yamada et al. Jan 1996 A
5536947 Klersy et al. Jul 1996 A
5625587 Peng et al. Apr 1997 A
5719416 Yoshimori et al. Feb 1998 A
5835396 Zhang Nov 1998 A
5894135 Yamamoto et al. Apr 1999 A
5985757 Lee et al. Nov 1999 A
5991193 Gallagher et al. Nov 1999 A
6034882 Johnson et al. Mar 2000 A
6128214 Kuekes et al. Oct 2000 A
6140672 Arita et al. Oct 2000 A
6185121 O'Neill Feb 2001 B1
6185122 Johnson et al. Feb 2001 B1
6204139 Liu et al. Mar 2001 B1
6236076 Arita et al. May 2001 B1
6259644 Tran et al. Jul 2001 B1
6326671 Nagano et al. Dec 2001 B1
6351406 Johnson et al. Feb 2002 B1
6385074 Johnson et al. May 2002 B1
6407953 Cleeves Jun 2002 B1
6420215 Knall et al. Jul 2002 B1
6458621 Beck Oct 2002 B1
6459095 Heath et al. Oct 2002 B1
6473332 Ignatiev et al. Oct 2002 B1
6487106 Kozicki Nov 2002 B1
6504753 Scheuerlein et al. Jan 2003 B1
6515888 Johnson et al. Feb 2003 B2
6515904 Moore et al. Feb 2003 B2
6522594 Scheuerlein Feb 2003 B1
6525953 Johnson Feb 2003 B1
6528365 Nagano et al. Mar 2003 B2
6531371 Hsu et al. Mar 2003 B2
6534403 Cleeves Mar 2003 B2
6545891 Tringali et al. Apr 2003 B1
6569745 Hsu May 2003 B2
6599796 Mei et al. Jul 2003 B2
6631085 Kleveland et al. Oct 2003 B2
6635603 Batlogg et al. Oct 2003 B1
6642539 Ramesh et al. Nov 2003 B2
6657888 Doudin et al. Dec 2003 B1
6693821 Hsu et al. Feb 2004 B2
6731528 Hush et al. May 2004 B2
6753561 Rinderson et al. Jun 2004 B1
6759249 Zhuang et al. Jul 2004 B2
6774054 Zhang Aug 2004 B1
6777248 Nabatame et al. Aug 2004 B1
6778420 Parkinson Aug 2004 B2
6788576 Roizin Sep 2004 B2
6807088 Tsuchida Oct 2004 B2
6816410 Kleveland et al. Nov 2004 B2
6822903 Scheuerlein et al. Nov 2004 B2
6825489 Kozicki Nov 2004 B2
6834013 Fan et al. Dec 2004 B2
6836421 Rinerson et al. Dec 2004 B2
6839269 Iwata et al. Jan 2005 B2
6850455 Rinerson et al. Feb 2005 B2
6855647 Beck et al. Feb 2005 B2
6856536 Rinerson et al. Feb 2005 B2
6859382 Rinerson et al. Feb 2005 B2
6882553 Nejad et al. Apr 2005 B2
6903361 Gilton Jun 2005 B2
6917539 Rinerson et al. Jul 2005 B2
6927430 Hsu Aug 2005 B2
6937505 Morikawa Aug 2005 B2
6939724 Zhuang et al. Sep 2005 B2
6940113 Hsu et al. Sep 2005 B2
6940744 Rinerson et al. Sep 2005 B2
6965137 Kinney et al. Nov 2005 B2
6970375 Rinerson et al. Nov 2005 B2
6972427 Roehr et al. Dec 2005 B2
6985378 Kozicki Jan 2006 B2
6998698 Inoue et al. Feb 2006 B2
7001846 Hsu Feb 2006 B2
7002197 Pemer et al. Feb 2006 B2
7005717 Eisenbeiser et al. Feb 2006 B2
7009909 Rinerson et al. Mar 2006 B2
7020006 Chevallier et al. Mar 2006 B2
7022572 Scheuerlein et al. Apr 2006 B2
7023743 Nejad et al. Apr 2006 B2
7029924 Hsu et al. Apr 2006 B2
7046550 Reohr et al. May 2006 B1
7057914 Rinerson et al. Jun 2006 B2
7060586 Li et al. Jun 2006 B2
7075817 Rinerson et al. Jul 2006 B2
7079442 Rinerson et al. Jul 2006 B2
7082052 Rinerson et al. Jul 2006 B2
7139667 Rothman et al. Nov 2006 B2
7141481 Hsu et al. Nov 2006 B2
7148533 Hsu et al. Dec 2006 B2
7177181 Scheuerlein Feb 2007 B1
7188534 Tombs et al. Mar 2007 B2
7227775 Rinerson et al. Jun 2007 B2
7256415 Furukawa et al. Aug 2007 B2
7292957 Schell Nov 2007 B1
7326979 Rinerson et al. Feb 2008 B2
7339811 Nejad et al. Mar 2008 B2
7360453 Rieder et al. Apr 2008 B2
7363800 Gysling Apr 2008 B2
7372753 Rinerson et al. May 2008 B1
7379364 Siau et al. May 2008 B2
7394679 Rinerson et al. Jul 2008 B2
7394680 Toda et al. Jul 2008 B2
7400006 Rinerson et al. Jul 2008 B1
7405960 Cho et al. Jul 2008 B2
7408212 Luan et al. Aug 2008 B1
7411811 Inoue Aug 2008 B2
7412903 Rieder et al. Aug 2008 B2
7417271 Genrikh et al. Aug 2008 B2
7433222 Hosoi et al. Oct 2008 B2
7443711 Stewart et al. Oct 2008 B1
7457147 Rinerson et al. Nov 2008 B2
7460385 Gruber et al. Dec 2008 B2
7463546 Fasoli et al. Dec 2008 B2
7464621 Mathis et al. Dec 2008 B2
7498600 Cho et al. Mar 2009 B2
7505344 Scheuerlein Mar 2009 B2
7508695 Sugita Mar 2009 B2
7538338 Rinerson et al. May 2009 B2
7554873 Lee et al. Jun 2009 B2
7608467 Wu et al. Oct 2009 B2
7633790 Rinerson et al. Dec 2009 B2
7639521 Baek et al. Dec 2009 B2
7643344 Choi Jan 2010 B2
7701791 Rinerson et al. Apr 2010 B2
7706177 Petti Apr 2010 B2
7719876 Chevallier et al. May 2010 B2
7733685 Scheuerlein et al. Jun 2010 B2
7742323 Rinerson et al. Jun 2010 B2
7782650 Bertin et al. Aug 2010 B2
7842991 Cho et al. Nov 2010 B2
7884349 Rinerson et al. Feb 2011 B2
7889539 Rinerson et al. Feb 2011 B2
7898841 Chevallier et al. Mar 2011 B2
7902867 Mouttet Mar 2011 B2
7902868 Norman Mar 2011 B2
7902869 Carter Mar 2011 B1
7924608 Campbell Apr 2011 B2
7929345 Issaq Apr 2011 B2
7955871 Wu et al. Jun 2011 B2
7961494 Scheuerlein Jun 2011 B2
7983065 Samachisa Jul 2011 B2
7985963 Rinerson et al. Jul 2011 B2
8062942 Rinerson et al. Nov 2011 B2
8139409 Chevallier et al. Mar 2012 B2
8482958 Hayakawa et al. Jul 2013 B2
8675389 Chevallier et al. Mar 2014 B2
8891276 Siau et al. Nov 2014 B2
8937292 Bateman Jan 2015 B2
9159408 Chevallier et al. Oct 2015 B2
9570515 Chevallier et al. Feb 2017 B2
9806130 Chevallier et al. Oct 2017 B2
20010055838 Walker et al. Dec 2001 A1
20030003674 Hsu et al. Jan 2003 A1
20030003675 Hsu Jan 2003 A1
20030043633 Forbes et al. Mar 2003 A1
20030132456 Miyai et al. Jul 2003 A1
20030137869 Kozicki Jul 2003 A1
20030148545 Zhuang et al. Aug 2003 A1
20030151959 Tringali et al. Aug 2003 A1
20030156445 Zhuang et al. Aug 2003 A1
20040109353 Matsuoka Jun 2004 A1
20040141369 Noguchi Jul 2004 A1
20040159828 Rinerson et al. Aug 2004 A1
20040159867 Kinney et al. Aug 2004 A1
20040159868 Rinerson et al. Aug 2004 A1
20040159869 Rinerson et al. Aug 2004 A1
20040161888 Rinerson et al. Aug 2004 A1
20040170040 Rinerson et al. Sep 2004 A1
20040180507 Zhang et al. Sep 2004 A1
20050018516 Chevallier et al. Jan 2005 A1
20050135148 Chevallier et al. Jun 2005 A1
20050151156 Wu Jul 2005 A1
20050174835 Rinerson et al. Aug 2005 A1
20050243595 Rinerson et al. Nov 2005 A1
20050269626 Forbes Dec 2005 A1
20060018149 Rinerson et al. Jan 2006 A1
20060023497 Kawazoe et al. Feb 2006 A1
20060050598 Rinerson et al. Mar 2006 A1
20060054937 Lucovsky et al. Mar 2006 A1
20060131695 Kuekes et al. Jun 2006 A1
20060171200 Rinerson et al. Aug 2006 A1
20060245241 Rinerson et al. Nov 2006 A1
20060245243 Rinerson et al. Nov 2006 A1
20070223282 Sarig Sep 2007 A1
20070253245 Ranjan et al. Nov 2007 A1
20080068875 Choi Mar 2008 A1
20080079029 Williams Apr 2008 A1
20080090337 Williams Apr 2008 A1
20080090401 Bratkovski et al. Apr 2008 A1
20080157127 Bertin et al. Jul 2008 A1
20080173975 Chen et al. Jul 2008 A1
20080278989 Lee et al. Nov 2008 A1
20080293196 Rinerson et al. Nov 2008 A1
20090027976 Brewer et al. Jan 2009 A1
20090045390 Rinerson et al. Feb 2009 A1
20090154232 Norman Jun 2009 A1
20090225582 Schloss Sep 2009 A1
20090302315 Lee et al. Dec 2009 A1
20090303772 Rinerson et al. Dec 2009 A1
20090303773 Rinerson et al. Dec 2009 A1
20100044666 Baek et al. Feb 2010 A1
20100067279 Choi Mar 2010 A1
20100073990 Siau et al. Mar 2010 A1
20100078759 Sekar et al. Apr 2010 A1
20100103724 Kim et al. Apr 2010 A1
20100110771 Choi May 2010 A1
20100134239 Wu et al. Jun 2010 A1
20100155686 Bratkovski et al. Jun 2010 A1
20100155722 Meyer Jun 2010 A1
20100155953 Bornstein Jun 2010 A1
20100157657 Rinerson et al. Jun 2010 A1
20100157658 Schloss et al. Jun 2010 A1
20100159641 Rinerson et al. Jun 2010 A1
20100159688 Rinerson et al. Jun 2010 A1
20100161888 Eggleston Jun 2010 A1
20100161918 Norman Jun 2010 A1
20100195393 Eggleston Aug 2010 A1
20100202188 Rinerson et al. Aug 2010 A1
20100271885 Scheuerlein et al. Oct 2010 A1
20100278479 Bratkovski et al. Nov 2010 A1
20100290294 Siau Nov 2010 A1
20110006275 Roelofs et al. Jan 2011 A1
20110017977 Bratkovski et al. Jan 2011 A1
20110024710 Bratkovski et al. Feb 2011 A1
20110024716 Bratkovski et al. Feb 2011 A1
20110059576 Cho et al. Mar 2011 A1
20110182103 Smythe et al. Jul 2011 A1
20110186803 Rinerson et al. Aug 2011 A1
20110188281 Siau et al. Aug 2011 A1
20110188282 Chevallier et al. Aug 2011 A1
20110188283 Chevallier et al. Aug 2011 A1
20110188284 Chevallier et al. Aug 2011 A1
20110297927 Ramaswamy et al. Dec 2011 A1
20120012897 Besser et al. Jan 2012 A1
20120033481 Rinerson et al. Feb 2012 A1
20120064691 Rinerson et al. Mar 2012 A1
20120087174 Rinerson et al. Apr 2012 A1
20120147678 Norman Jun 2012 A1
20130043452 Meyer et al. Feb 2013 A1
Foreign Referenced Citations (9)
Number Date Country
1376598 Jan 2004 EP
1376598 Jun 2006 EP
2003-092387 Mar 2003 JP
2004-193595 Jul 2004 JP
2005-203733 Jul 2005 JP
0048196 Aug 2000 WO
03079463 Sep 2003 WO
2005117021 Dec 2005 WO
2006029228 Mar 2006 WO
Non-Patent Literature Citations (163)
Entry
Notice of Allowance dated Feb. 22, 2022, issued in related U.S. Appl. No. 17/028,909 (8 pages).
Non-Final Office Action dated Oct. 6, 2010, issued in related U.S. Appl. No. 12/283,339 (7 pages).
Notice of Allowance dated Dec. 29, 2010, issued in related U.S. Appl. No. 12/283,339 (6 pages).
Non-Final Office Action dated Sep. 3, 2020, issued in related U.S. Appl. No. 16/864,051 (24 pages).
Non-Final Office Action dated Sep. 15, 2021, issued in related U.S. Appl. No. 17/028,909 (9 pages).
Abelmann et al., “Self-Assembled Three-Dimensional Non-Volatile Memories,” Micromachines 2010, vol. 1, pp. 1-18, Jan. 18, 2010. 18 pages.
Baek et al., “Realization of Vertical Resistive Memory (VRRAM) Using Cost Effective 3D Process,” IDEM 2011, 318.1, pp. 737-740. 4 pages.
Baikalov et al., “Field-Driven Hysteretic and Reversible Resistive Switch at the Ag-Pr0.7Ca0.3Mn03 3 Interface,” Applied Physics Letters, vol. 83, No. 5, Aug. 4, 2003, pp. 957-959. 3 pages.
Bateman, Bruce, U.S. Appl. No. 13/210,292, filed Aug. 15, 2011, re Filed Application with Figures. 88 pages.
Beck et al., “Reproducible Switching Effect in Thin Oxide Films for Memory Applications,” Applied Physics Letters, vol. 77, No. 1, Jul. 3, 2000, pp. 139-141. 3 pages.
Brewer, Julie, U.S. Appl. No. 13/210,342, filed Aug. 15, 2011, re Filed Application and Figures, 81 pages.
Chevallier et al., “A 0.13um 64Mb Multi-layered Conductive Metal-Oxide Memory,” ISSCC 2010/Session 14/Non-Volatile Memory/ 14.3, pp. 260-261. 2 pages.
Crowley et al., “16.4: 512Mb PROM with 8 Layers of Antifuse/Diode Cells,” 2003 IEEE ISSCC, First Edition, pp. 284-285, 493, Feb. 11, 2003. 10 pages.
Dong et al., ““Si/a-Si Core/Shell Nanowires as Nonvolatile Crossbar Switches,”” Nano Letters 2008, vol. 8, No. 29 pp. 861-391. 6 pages.
EP Office Action dated Aug. 2, 2007 in EP 05794930.7. 4 pages.
Jang et al., “Vertical Cell Array Using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density 11 NAND Flash Memory,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193. 2 pages.
JP Response dated Aug. 7, 2012 re JP Application No. 2007-530487. 9 pages.
Katsumata et al,, “Pipe-Shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 136-137. 2 pages.
Kim et al., “Novel Vertical-Stacked-Array-Transistor (VSAT) for Ultra-High-Density and Cost-Effective NAND Flash Memory Device and SSD (Solid State Drive),” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187. 2 pages.
Kim et al., “Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage,” 2009 VLSI Symposium on VLSI Technology Digest of Technical Papers, Jun. 16-18, 2009, pp. 188-189. 2 pages.
Krieger, Ju H., “Principle Operation of 3-D Memory Device based on Piezoacousto Properties of Ferroelectric Films,” In Tech, Dec. 2010, pp. 3-16. 14 pages.
Kwong et al., “Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications,” May 25, 2011, Journal of Nanotechnology, vol. 2012, Article ID 492121. 21 pages.
Lai et al., “OUM-A 180 nm Nanvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications,” IEEE International Electron Device Meeting, Technical Digest, 2001. 4 pages.
Lee et la., “Near Edge X-ray Absorption Fine Structure Study of Pr0.65Ca0.35Mn03 Films,” Phys. Stat, sol (a) 196, No. 1, 2003, pp. 70-73. 4 pages.
Liu et al., “A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films,” Non-Volatile Memory Technology Symposium, Nov. 7, 2001, pp. 1-7. 7 pages.
Liu et al., “Electric-Pulse-Induced Reversible Resistance Change Effect in Magnetoresistive Films,” Applied Physics Letters, vol. 76, No. 19, May 8, 2000, pp. 2749-2751. 3 pages.
Lue et al., “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” 2010 Symposium on VLSI Technology, Jun. 15-17, 2010, pp. 131-132. 2 pages.
Millis, A.J., “Cooperative Jahn-Teller Effect and Electron-Phonon Coupling in La-1-xAxMn03”, Phys. Rev. B 53 8434-8441 (1996). 8 pages.
Mizusaki, J., et al., “Electronic Conductivity, Seebeck Coefficient, Defect and Electronic Structure of Nonstoichiometric La1-xSRxMn03”, Solid State Ionics 132, pp. 167-180 (2000). 14 pages.
Nian, Y.B., et al.,“Evidence for an Oxygen Diffusion Model for the Electric Pulse Induced Resistance Change Effect in Oxides”, Texas Center for Advanced Materials, University of Houston (2006). 7 pages.
Oligschlaeger, R.,et al., “Resistive Switching and Data Reliability of Epitaxial (Ba,Sr) TiO thin films,” Applied Physics Letters, 88 (2006), 042901. 3 pages.
Ou et al., “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Memory,” Doctoral Dissertation, Standford University, Mar. 2010, pp. 1-119. 119 pages.
Ou et la., “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory,” IEEE Journal of Solid-State Circuits, vol. 46, No. 9, Sep. 2011, pp. 2158-2170. 13 pages.
Oxley, David, “Chapter 4: Memory Effects in Oxide Films,” pp. 251-325 in Oxides and Oxide Films, vol. 6, 1981, edited by Ashok K. Vijh. 39 pages.
Parrillo, Louis, U.S. Appl. No. 13/250,772, filed Sep. 30, 2011, re Filed Application with Figures. 63 pages.
PCT—International Preliminary Report on Patentablility on PCT/US05/031913, dated Aug. 28, 2007. 5 pages.
PCT—International Search Report for PCT/US05/031913, dated Feb. 14, 2006. 6 pages.
PCT—Written Opinion of ISA on PCT/US05/031913, dated May 24, 2006. 7 pages.
PCT International Search Report and Written Opinion dated Aug. 15, 2006 in International Application No. PCT/US05/31913. 14 pages.
Reller et al., “Superstrucutres Formed by the Ordering of Vacancies in a Selective Oxidation Catalyst: Grossly Defective CaMn03,” Proceedings of the Royal Society of London, vol. 394, No. 1807, Aug. 1984, pp. 223-241. 26 pages.
Reller, A. et al., “Superstructures Formed by the Ordering of Vacancies in a Selective Oxidation Catalyst: Grossly Defective CaMn03”, Printed in Great Britain, Department of Physical Chemistry, University of Cambridge, Lensfield Road, Cambridge, CB2 1EP, U.K., vol. 194. Aug. 8, 1984. 1 page.
Rossel, et al., “Electrical Current Distribution Across a Metal-Insulator-metal Structure During Bistable Switching,” Journal of Applied Physics, vol. 90, No. 6, Sep. 15, 2001, pp. 2892-2898. 7 pages.
Sawa et al., “Hysteretic Current-Voltage Characteristics and Resistance Switching at a Rectifying Ti/Pr0.7Ca0.3Mn03 Interface,” Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4073-4075. 3 pages.
Siau, Chang, U.S. Appl. No. 13/134,579, filed Jun. 10, 2011, re Filed Application with Figures. 64 pages.
Simmons et al., “New Conduction and Reversible Memory Phenomena in Thin Insulating Films,” Proceedings of the Royal Society of London, vol. 301, No. 1464, Oct. 3, 1967, pp. 777-102. 28 pages.
Steele, B.C.H., et al., “Materials for Fuel-Cell Technologies,” Nature 414, Nov. 2001, pp. 345-352, 9 pages.
Stetter, J.R., et al., “Sensors, Chemical Sensors, Electrochemical Sensors, and ECS”, Journal of Electrochemical Society, 150 (2), S11-S16 (2003). 6 pages.
Strachan et al., “The Switching Location of a Bipolar Memristor: Chemical, Thermal and Structural Mapping,” Nanotechnology 22 (2011) 254015, pp. 1-6. 7 pages.
Thurstans et al., “The Electroformed Metal-Insulator-Metal Structure: A Comprehensive Model,” Journal of Physics D: Applied Physics, J. Phys. D: Appl. Phys. 35 (2002), Apr. 2, 2002, pp. 802-809. 8 pages.
Watanabe et al., “Current-Driven Insulator-Conductor Transition and Nonvolatile Memory in Chromium-Doped SrTi03 Single Crystals,” Applied Physics Letters, vol. 78, No. 23, Jun. 4, 2001, pp. 3738-3740. 3 pages.
Wu, Jian, U.S. Appl. No. 13/250,923, filed Sep. 30, 2011, re Filed Application with Figures. 44 pages.
Yoon et al., “Vertical Cross-point Resistance Change Memory for Ultra-High Density Non-Volatile Memory Applications,” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 26-27. 2 pages.
Zhang et al., “A 3D RRAM Using Stackable 1TXR Memory Cell for High Density Application,” IEEE Xplore, Feb. 5, 2010, pp. 917-920. 4 pages.
Zhao, Y.G., et al., “Effect of Oxygen Content on the Structural, Transport, and Magnetic Properties of La 1-deltaMn 1-delta03 thin films,” Journal of Applied Physics, vol. 86, No. 11, Dec. 1999, pp. 6327-6330. 4 pages.
Notice of Allowance dated Mar. 30, 2021, issued in related U.S. Appl. No. 16/864,051 (8 pages).
Viktor V. Poltavets, “Charge transfer, hybridization and local inhomogeneity effects in NaxCoO2*yH2O”, Phys. Rev. B 74 (2006), pp. 1-4.
Gloria Subias et al., “Mn local structure effects in charge-ordered mixed-valence RE1-xCaxMnO3 (RE:La, Tb) perovskites: a review of the experimental situation”, Journal of Physics: Condensed Matter, Issue 19, May 20, 2002, Abstract.
Hisao Yamauchi et al., “Control of mixed valence state to yield novel functions in double-perovskite iron-copper oxides”, Science Links Japan, Nippon Sheet Glass Foundation for Materials Science and Engineering Report, 2003, Abstract.
First Search dated Jan. 11, 2009, issued in related Chinese Application No. 200580038024.5 (1 page).
Supplementary Search dated Mar. 29, 2010, issued in related Chinese Application No. 200580038024.5 (1 page).
Supplementary Search dated Mar. 2, 2011, issued in related Chinese Application No. 200580038024.5 (1 page).
First Office Action dated Jan. 6, 2014, issued in related Chinese Application No. 201210193421.1, with English machine translation (7 pages).
Examination Report dated Jan. 25, 2010, issued in related European Application No. 05794930.7 (3 pages).
Extended European Search Report dated May 25, 2011, issued in related European Application No. 10182254.2 (5 pages).
Examination Report dated Dec. 13, 2013, issued in related European Application No. 10182254.2 (3 pages).
Notice of Reasons for Refusal dated Feb. 7, 2012, issued in related Japanese Application No. 2007-530487, with English machine translation (6 pages).
Final Notification of Reasons for Refusal dated Jan. 8, 2013, issued in related Japanese Application No. 2007-530487, with English machine translation (6 pages).
Decision of Refusal dated Aug. 13, 2013, issued in related Japanese Application No. 2007-530487, with English machine translation (2 pages).
Notification of Reason for Refusal dated Dec. 5, 2011, issued in related Korean Application No. 10-2007-7005463, with English machine translation (8 pages).
Grant of Patent dated Nov. 6, 2012, issued in related Korean Application No. 10-2007-7005463, with English machine translation (4 pages).
Non-Final Office Action dated Feb. 1, 2007, issued in related U.S. Appl. No. 10/934,951 (19 pages).
Non-Final Office Action dated Jan. 7, 2008, issued in related U.S. Appl. No. 11/095,026 (7 pages).
Final Office Action dated May 5, 2009, issued in related U.S. Appl. No. 11/095,026 (6 pages).
Notice of Allowance dated Sep. 24, 2007, issued in related U.S. Appl. No. 11/473,005 (8 pages).
Non-Final Office Action dated Mar. 23, 2009, issued in related U.S. Appl. No. 11/681,992 (5 pages).
Notice of Allowance dated Nov. 20, 2009, issued in related U.S. Appl. No. 11/681,992 (7 pages).
Notice of Allowance dated Oct. 11, 2011, issued in related U.S. Appl. No. 12/215,958 (10 pages).
Non-Final Office Action dated Jun. 26, 2009, issued in related U.S. Appl. No. 12/286,723 (8 pages).
Non-Final Office Action dated Jan. 11, 2011, issued in related U.S. Appl. No. 12/456,627 (6 pages).
Final Office Action dated Jun. 1, 2011, issued in related U.S. Appl. No. 12/456,627 (5 pages).
Non-Final Office Action dated Aug. 21, 2013, issued in related U.S. Appl. No. 12/456,627 (7 pages).
Non-Final Office Action dated Mar. 12, 2014, issued in related U.S. Appl. No. 12/456,627 (9 pages).
Non-Final Office Action dated Jan. 14, 2011, issued in related U.S. Appl. No. 12/456,677 (6 pages).
Final Office Action dated Jun. 2, 2011, issued in related U.S. Appl. No. 12/456,677 (5 pages).
Notice of Allowance dated Dec. 30, 2010, issued in related U.S. Appl. No. 12/653,486 (9 pages).
Notice of Allowance dated Oct. 17, 2012, issued in related U.S. Appl. No. 12/931,967 (6 pages).
Notice of Allowance dated Oct. 28, 2013, issued in related U.S. Appl. No. 13/272,985 (10 pages).
Notice of Allowance dated Sep. 5, 2013, issued in related U.S. Appl. No. 13/301,490 (10 pages).
Non-Final Office Action dated Sep. 6, 2012, issued in related U.S. Appl. No. 13/329,063 (9 pages).
Notice of Allowance dated Jun. 10, 2015, issued in related U.S. Appl. No. 14/167,694 (10 pages).
Notice of Allowance dated Jun. 15, 2015, issued in related U.S. Appl. No. 14/463,518 (9 pages).
Non-Final Office Action dated Jun. 30, 2016, issued in related U.S. Appl. No. 14/850,702 (6 pages).
Non-Final Office Action dated Feb. 2, 2016, issued in related U.S. Appl. No. 14/844,805 (11 pages).
Final Office Action dated Jun. 3, 2016, issued in related U.S. Appl. No. 14/844,805 (14 pages).
Non-Final Office Action dated Oct. 6, 2016, issued in related U.S. Appl. No. 14/844,805 (15 pages).
Final Office Action dated Feb. 7, 2017, issued in related U.S. Appl. No. 14/844,805 (15 pages).
Non-Final Office Action dated Mar. 23, 2017, issued in related U.S. Appl. No. 15/393,545 (11 pages).
Non-Final Office Action dated Jun. 11, 2018, issued in related U.S. Appl. No. 15/797,452 (10 pages).
Notice of Allowance dated Oct. 17, 2018, issued in related U.S. Appl. No. 14/844,805 (8 pages).
Non-Final Office Action dated Oct. 18, 2018, issued in related U.S. Appl. No. 15/797,716 (10 pages).
Non-Final Office Action dated Feb. 10, 2020, issued in related U.S. Appl. No. 16/412,015 (10 pages).
Rinerson, Darrell, U.S. Appl. No. 11/473,005, filed Jun. 22, 2006, Response dated Sep. 5, 2007 to the Office Action dated Aug. 23, 2007. 12 pages.
Rinerson, Darrell, U.S. Appl. No. 12/215,958, filed Jun. 30, 2008, Notice of Allowance and Fee(s) Due dated Oct. 11, 2011. 14 pages.
Rinerson, Darrell, U.S. Appl. No. 12/215,958, filed Jun. 30, 2008, Office Action dated Jul. 25, 2011 re Restriction Requirement. 6 pages.
Rinerson, Darrell, U.S. Appl. No. 12/215,958. filed Jun. 30, 2008, Response dated Jul. 27, 2011 to the Restriction Requirement dated Jul. 25, 2011. 10 pages.
Rinerson, Darrell, U.S. Appl. No. 12/286,723, filed Oct. 1, 2008, Notice of Allowance and Fee(s) Due dated Oct. 6, 2009. 8 pages.
Rinerson, Darrell, U.S. Appl. No. 12/286,723, filed Oct. 1, 2008, Office Action dated Jun. 26, 2009. 9 pages.
Rinerson, Darrell, U.S. Appl. No. 12/286,723, filed Oct. 1, 2008, Response dated Jul. 30, 2009 to the Office Action dated Jun. 26, 2009. 8 pages.
Rinerson, Darrell, U.S. Appl. No. 12/653,486, filed Dec. 14, 2009, Notice of Allowance and Fee(s) Due dated Dec. 30, 2010. 12 pages.
Rinerson, Darrell, U.S. Appl. No. 12/653,486, filed Dec. 14, 2009, Notice to File Corrected Application Papers dated Feb. 23, 2010. 2 pages.
Rinerson, Darrell, U.S. Appl. No. 12/653,486, filed Dec. 14, 2009, Reply dated Feb. 25, 2010 to the Notice to File Corrected Application Papers of Feb. 23, 2010. 7 pages.
Notice of Allowance dated Feb. 6, 2020, issued in related U.S. Appl. No. 16/262,841 (8 pages).
Non-Final Office Action dated Oct. 7, 2019, issued in related U.S. Appl. No. 16/262,841 (9 pages).
Zhung, W.W. et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM Technical Digest, IEEE, Dec. 8, 2002, pp. 193-196. 4 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Preliminary Amendment dated Sep. 12, 2005. 10 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Office Action dated Jun. 15, 2007. 6 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filled Mar. 30, 2005 re Response to Restriction Requirement dated Jul. 5, 2007. 9 pages.
Chevallier, Christophe, U.S. Appl. No. 12/658,138, filed Feb. 2, 2010, Office Action dated Feb. 3, 2012 re Restriction Requirement. 5 pages.
Chevallier, Christophe, U.S. Appl. No. 12/658,138, filed Feb. 2, 2010, Response dated Feb. 15, 2012 to the Restriction Requirement of Feb. 3, 2012. 19 pages.
Chevallier, Christophe, U.S. Appl. No. 12/658,138, filed Feb. 2, 2010, Office Action dated Mar. 20, 2012. 58 pages.
Siau, Chang, U.S. Appl. No. 12/657,911, filed Jan. 29, 2010, Office Action dated Feb. 6, 2012. 37 pages.
Siau, Chang, U.S. Appl. No. 12/657,911, filed Jan. 29, 2010, Office Action dated Dec. 15, 2011 re Restriction Requirement. 6 pages.
Siau, Chang, U.S. Appl. No. 12/657,911, filed Jan. 29, 2010, Response to dated Dec. 15, 2011 to the Restriction Requirement dated Dec. 15, 2011. 13 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Office Action dated Sep. 27, 2007. 5 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Response to Restriction Requirement dated Oct. 22, 2007. 9 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Office Action dated Jan. 7, 2008. 15 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Amendment and Response dated Aug. 26, 2008. 15 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Office Action dated Sep. 3, 2008. 3 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Final Office Action dated May 5, 2009. 6 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Appeal Brief dated Aug. 7, 2009. 41 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Amended Appeal Brief dated Jan. 6, 2010. 59 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 11/095,026, filed Mar. 30, 2005 re Office Action dated Jul. 12, 2010. 10 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 12/456,677, filed Jun. 18, 2009, Office Action dated Jan. 14, 2011. 6 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 12/456,677, filed Jun. 18, 2009, Reply & Amendment dated Mar. 25, 2011. 14 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 12/456,677, filed Jun. 18, 2009, Final Office Action dated Jun. 2, 2011. 3 pages.
Rinerson, Darrell, et al., U.S. Appl. No. 10/985,218, filed Jan. 12, 2004, re U.S. Appl. No. 60/536,115, filed Jan. 13, 2004. 9 pages.
Siau, Chang, U.S. Appl. No. 12/657,911, filed Jan. 29, 2010, Response dated May 7, 2012 to the Office Action dated Feb. 6, 2012. 18 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Office Action dated Jun. 15, 2006. 15 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Preliminary Amendemn tsubmitted Oct. 12, 2006. 8 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Interview Summary dated Oct. 13, 2006. 3 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Office Action dated Feb. 1, 2007. 8 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Response dated Mar. 1, 2007 to the Office Action dated Feb. 1, 2007. 39 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Final Office Action dated May 25, 2007. 7 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Pre-Appeal Brief Request for Review dated Oct. 25, 2007. 6 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Appeal Brief dated Jun. 9, 2008. 48 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Office Action dated Sep. 2, 2008. 9 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Response dated Dec. 22, 2008 to the Office Action dated Sep. 2, 2008. 25 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Final Office Aciton dated Mar. 10, 2009. 7 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Response dated Mar. 11, 2009 to the Final Office Action dated Mar. 10, 2009. 8 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Notice of Allowance and Fee(s) Due dated Mar. 25, 2009. 12 pages.
Rinerson, Darrell, U.S. Appl. No. 10/934,951, filed Sep. 3, 2004, Supplemental Notice of Allowability. 3 pages.
Chemical Elements.com, “Periodic Table: Transition Metals”, 1996, downloaded0 Mar. 19, 2017 from http://www.chemicalelements.com/groups/transition.html. 2 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Notice of Allowance and Fee(s) Due dated Mar. 7, 2006. 10 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Office Action dated Nov. 29, 2005. 16 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Office Action dated May 4, 2005 re Restriction Requirement. 6 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Office Action dated Aug. 24, 2005 re Restriction Requirement. 7 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Proposal submitted Feb. 1, 2006 for Amending Drawing(s) in Repsonse to Office Action dated Nov. 29, 2005. 11 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Response dated Feb. 23, 2006 to the Office Action of Nov. 29, 2006. 16 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Response dated Jun. 6, 2005 to the Restriction Requirement dated May 4, 2005. 3 pages.
Rinerson, Darrell, U.S. Appl. No. 10/773,549, filed Feb. 6, 2004, Response dated Sep. 9, 2005 to the Restriction Requirement dated Aug. 24, 2005. 5 pages.
Rinerson, Darrell, U.S. Appl. No. 11/473,005, filed Jun. 22, 2006, Notice of Allowance and Fee(s) due dated Sep. 24, 2007. 13 pages.
Rinerson, Darrell, U.S. Appl. No. 11/473,005, filed Jun. 22, 2006, Office Action dated Aug. 23, 2007. 7 pages.
Rinerson, Darrell, U.S. Appl. No. 11/473,005, filed Jun. 22, 2006, Preliminary Amendment dated Jul. 25, 2006. 12 pages.
Related Publications (1)
Number Date Country
20210193917 A1 Jun 2021 US
Continuations (7)
Number Date Country
Parent 16864051 Apr 2020 US
Child 17194609 US
Parent 16262841 Jan 2019 US
Child 16864051 US
Parent 15797452 Oct 2017 US
Child 16262841 US
Parent 14844805 Sep 2015 US
Child 15797452 US
Parent 14463518 Aug 2014 US
Child 14844805 US
Parent 12456627 Jun 2009 US
Child 14463518 US
Parent 11095026 Mar 2005 US
Child 12456627 US
Continuation in Parts (2)
Number Date Country
Parent 10934951 Sep 2004 US
Child 11095026 US
Parent 10773549 Feb 2004 US
Child 10934951 US