David Chiang

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Indexing using contiguous, non-overlapping ranges
- Patent number 7,962,489
- Issue date Jun 14, 2011
- Sage-N Research, Inc.
- David Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for efficient pattern match operations
- Patent number 7,464,088
- Issue date Dec 9, 2008
- Sage-N Research, Inc.
- David Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus-hold circuit having a defined state during set-up of an in-syst...
- Patent number 6,172,519
- Issue date Jan 9, 2001
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programming method to enable system recovery after power failure
- Patent number 6,018,250
- Issue date Jan 25, 2000
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Carry chain circuit with flexible carry function for implementing a...
- Patent number 5,898,602
- Issue date Apr 27, 1999
- Xilinx, Inc.
- Daniel J. Rothman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated control system for programming PLDs
- Patent number 5,784,577
- Issue date Jul 21, 1998
- Neil G. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for partially reprogramming an operational programmable log...
- Patent number 5,764,076
- Issue date Jun 9, 1998
- Xilinx, Inc.
- Napoleon W. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable voltage stabilizing circuit for a programmable integra...
- Patent number 5,742,178
- Issue date Apr 21, 1998
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexed by-passable memory devices with increased speed and imp...
- Patent number 5,570,051
- Issue date Oct 29, 1996
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Macrocell with product-term cascade and improved flip flop utilization
- Patent number 5,565,792
- Issue date Oct 15, 1996
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cross point interconnect structure with reduced area
- Patent number 5,530,378
- Issue date Jun 25, 1996
- Xilinx, Inc.
- Nicholas Kucharewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Antifuse-based programmable logic circuit
- Patent number 5,506,518
- Issue date Apr 9, 1996
- Xilinx, Inc.
- David Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense circuit with selectable zero power single input function mode
- Patent number 5,506,523
- Issue date Apr 9, 1996
- Xilinx, Inc.
- David Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable clock having programmable delay and duty cycle based o...
- Patent number 5,506,878
- Issue date Apr 9, 1996
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Antifuse-based programmable logic circuit
- Patent number 5,486,776
- Issue date Jan 23, 1996
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and structure for reducing carry delay for a programmable ca...
- Patent number 5,483,478
- Issue date Jan 9, 1996
- Xilinx, Inc.
- David Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
EPLD chip with hybrid architecture optimized for both speed and fle...
- Patent number 5,450,021
- Issue date Sep 12, 1995
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer circuit having reduced switching noise
- Patent number 5,448,181
- Issue date Sep 5, 1995
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-density erasable programmable logic device architecture using...
- Patent number 5,384,499
- Issue date Jan 24, 1995
- Altera Corporation
- Bruce B. Pedersen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
EPLD chip with hybrid architecture optimized for both speed and fle...
- Patent number 5,362,999
- Issue date Nov 8, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Precharging bitlines for robust reading of latch data
- Patent number 5,361,229
- Issue date Nov 1, 1994
- Xilinx, Inc.
- David Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Macrocell with product-term cascade and improved flip flop utilization
- Patent number 5,357,153
- Issue date Oct 18, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having security elements located amongst...
- Patent number 5,349,249
- Issue date Sep 20, 1994
- Xilinx, Inc.
- David Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management for programmable logic devices
- Patent number 5,332,929
- Issue date Jul 26, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for forcing known voltage on unconnected pads of an integra...
- Patent number 5,329,174
- Issue date Jul 12, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input circuit block and method for PLDs with register clock enable...
- Patent number 5,302,866
- Issue date Apr 12, 1994
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-density erasable programmable logic device architecture using...
- Patent number 5,268,598
- Issue date Dec 7, 1993
- Altera Corporation
- Bruce B. Pedersen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-density erasable programmable logic device architecture using...
- Patent number 5,241,224
- Issue date Aug 31, 1993
- Altera Corporation
- Bruce B. Pedersen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for measuring gate delays in integrated circui...
- Patent number 5,097,208
- Issue date Mar 17, 1992
- Altera Corporation
- David Chiang
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for reducing coupling noise in programmable l...
- Patent number 5,091,661
- Issue date Feb 25, 1992
- Altera Corporation
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY

David Chiang

Person

Patents Grantslast 30 patents

Indexing using contiguous, non-overlapping ranges

Architecture for efficient pattern match operations

Bus-hold circuit having a defined state during set-up of an in-syst...

Programming method to enable system recovery after power failure

Carry chain circuit with flexible carry function for implementing a...

Automated control system for programming PLDs

Circuit for partially reprogramming an operational programmable log...

Programmable voltage stabilizing circuit for a programmable integra...

Multiplexed by-passable memory devices with increased speed and imp...

Macrocell with product-term cascade and improved flip flop utilization

Cross point interconnect structure with reduced area

Antifuse-based programmable logic circuit

Sense circuit with selectable zero power single input function mode

Programmable clock having programmable delay and duty cycle based o...

Antifuse-based programmable logic circuit

Method and structure for reducing carry delay for a programmable ca...

EPLD chip with hybrid architecture optimized for both speed and fle...

Output buffer circuit having reduced switching noise

High-density erasable programmable logic device architecture using...

EPLD chip with hybrid architecture optimized for both speed and fle...

Precharging bitlines for robust reading of latch data

Macrocell with product-term cascade and improved flip flop utilization

Programmable logic device having security elements located amongst...

Power management for programmable logic devices

Circuit for forcing known voltage on unconnected pads of an integra...

Input circuit block and method for PLDs with register clock enable...

High-density erasable programmable logic device architecture using...

High-density erasable programmable logic device architecture using...

Apparatus and method for measuring gate delays in integrated circui...

Methods and apparatus for reducing coupling noise in programmable l...