David L. Pinney

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Ferroelectric memory plate power reduction
- Patent number 11,699,475
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for data movement
- Patent number 11,614,877
- Issue date Mar 28, 2023
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for partitioned parallel data movement
- Patent number 11,513,713
- Issue date Nov 29, 2022
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell voltage accumulation discharge
- Patent number 11,074,955
- Issue date Jul 27, 2021
- Micron Techology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory plate power reduction
- Patent number 10,998,026
- Issue date May 4, 2021
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for data movement
- Patent number 10,936,235
- Issue date Mar 2, 2021
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for partitioned parallel data movement
- Patent number 10,915,263
- Issue date Feb 9, 2021
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell voltage accumulation discharge
- Patent number 10,636,469
- Issue date Apr 28, 2020
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory plate power reduction
- Patent number 10,622,050
- Issue date Apr 14, 2020
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for data movement
- Patent number 10,365,851
- Issue date Jul 30, 2019
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for partitioned parallel data movement
- Patent number 10,324,654
- Issue date Jun 18, 2019
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing data in memory
- Patent number 10,304,502
- Issue date May 28, 2019
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Accessing data in memory
- Patent number 10,147,468
- Issue date Dec 4, 2018
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for partitioned parallel data movement
- Patent number 10,048,888
- Issue date Aug 14, 2018
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G11 - INFORMATION STORAGE
Information Patent Grant
Accessing data in memory
- Patent number 9,997,212
- Issue date Jun 12, 2018
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage sense amplifier and sensing method
- Patent number 7,986,578
- Issue date Jul 26, 2011
- Micron Technology, Inc.
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage sense amplifier and sensing method
- Patent number 7,626,877
- Issue date Dec 1, 2009
- Micron Technology, Inc.
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic well bias controlled by Vt detector
- Patent number 7,535,282
- Issue date May 19, 2009
- Micron Technology, Inc.
- Tae Kim
- G05 - CONTROLLING REGULATING
Information Patent Grant
Open digit line array architecture for a memory array
- Patent number 7,512,025
- Issue date Mar 31, 2009
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage sense amplifier and sensing method
- Patent number 7,505,341
- Issue date Mar 17, 2009
- Micron Technology, Inc.
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Open digit line array architecture for a memory array
- Patent number 7,345,937
- Issue date Mar 18, 2008
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Open digit line array architecture for a memory array
- Patent number 7,277,310
- Issue date Oct 2, 2007
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Open digit line array architecture for a memory array
- Patent number 7,254,074
- Issue date Aug 7, 2007
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Open digit line array architecture for a memory array
- Patent number 7,193,914
- Issue date Mar 20, 2007
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual stage DRAM memory equalization
- Patent number 7,038,958
- Issue date May 2, 2006
- Micron Technology, Inc.
- Yangsung Joo
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-test ram using external synchronous clock
- Patent number 6,684,356
- Issue date Jan 27, 2004
- Micron Technology, Inc.
- George B. Raad
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for using complementary bits in a memory array
- Patent number 6,654,297
- Issue date Nov 25, 2003
- Micron Technology, Inc.
- David L. Pinney
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for using complementary bits in a memory array
- Patent number 6,549,476
- Issue date Apr 15, 2003
- Micron Technology, Inc.
- David L. Pinney
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-test RAM using external synchronous clock
- Patent number 6,502,215
- Issue date Dec 31, 2002
- Micron Technology, Inc.
- George B. Raad
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit having improved sense-amplifier block and method for...
- Patent number 6,421,266
- Issue date Jul 16, 2002
- Micron Technology, Inc.
- David L. Pinney
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FERROELECTRIC MEMORY PLATE POWER REDUCTION
- Publication number 20210312967
- Publication date Oct 7, 2021
- Micro Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR DATA MOVEMENT
- Publication number 20210181969
- Publication date Jun 17, 2021
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
- Publication number 20210157503
- Publication date May 27, 2021
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL VOLTAGE ACCUMULATION DISCHARGE
- Publication number 20200219551
- Publication date Jul 9, 2020
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Application
FERROELECTRIC MEMORY PLATE POWER REDUCTION
- Publication number 20200211613
- Publication date Jul 2, 2020
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Application
FERROELECTRIC MEMORY PLATE POWER REDUCTION
- Publication number 20190348098
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Application
CELL VOLTAGE ACCUMULATION DISCHARGE
- Publication number 20190348099
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Adam S. El-Mansouri
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR DATA MOVEMENT
- Publication number 20190347031
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
- Publication number 20190272114
- Publication date Sep 5, 2019
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING DATA IN MEMORY
- Publication number 20190088291
- Publication date Mar 21, 2019
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
- Publication number 20180321871
- Publication date Nov 8, 2018
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESSING DATA IN MEMORY
- Publication number 20180308528
- Publication date Oct 25, 2018
- Micron Technology, Inc.
- Timothy P. Finkbeiner
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR DATA MOVEMENT
- Publication number 20180046405
- Publication date Feb 15, 2018
- Micron Technology, Inc.
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
- Publication number 20170228192
- Publication date Aug 10, 2017
- Micron Technology, Inc.
- Jeremiah J. Willcock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD
- Publication number 20100061158
- Publication date Mar 11, 2010
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD
- Publication number 20090168551
- Publication date Jul 2, 2009
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Open digit line array architecture for a memory array
- Publication number 20080137458
- Publication date Jun 12, 2008
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
Low voltage sense amplifier and sensing method
- Publication number 20070268764
- Publication date Nov 22, 2007
- Micron Technology, Inc.
- Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic well bias controlled by Vt detector
- Publication number 20060273842
- Publication date Dec 7, 2006
- Micron Technology, Inc.
- Tae Kim
- G05 - CONTROLLING REGULATING
Information Patent Application
Open digit line array architecture for a memory array
- Publication number 20060268640
- Publication date Nov 30, 2006
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
Open digit line array architecture for a memory array
- Publication number 20060268639
- Publication date Nov 30, 2006
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
Open digit line array architecture for a memory array
- Publication number 20060268638
- Publication date Nov 30, 2006
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
Open digit line array architecture for a memory array
- Publication number 20060198220
- Publication date Sep 7, 2006
- Micron Technology, Inc.
- Sei Seung Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
Dual stage DRAM memory equalization
- Publication number 20060152987
- Publication date Jul 13, 2006
- Yangsung Joo
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL STAGE DRAM MEMORY EQUALIZATION
- Publication number 20060044901
- Publication date Mar 2, 2006
- Yangsung Joo
- G11 - INFORMATION STORAGE
Information Patent Application
Self-test ram using external synchronous clock
- Publication number 20030065999
- Publication date Apr 3, 2003
- George B. Raad
- G11 - INFORMATION STORAGE
Information Patent Application
Device and method for using complementary bits in a memory array
- Publication number 20030043645
- Publication date Mar 6, 2003
- Micron Technology, Inc.
- David L. Pinney
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE AND METHOD FOR USING COMPLEMENTARY BITS IN A MEMORY ARRAY
- Publication number 20020145917
- Publication date Oct 10, 2002
- Micron Technology, Inc.
- David L. Pinney
- G11 - INFORMATION STORAGE
Information Patent Application
Self-test ram using external synchronous clock
- Publication number 20020040454
- Publication date Apr 4, 2002
- George B. Raad
- G11 - INFORMATION STORAGE
Information Patent Application
Equilibrate method for dynamic plate sensing memories
- Publication number 20010006482
- Publication date Jul 5, 2001
- David L. Pinney
- G11 - INFORMATION STORAGE

David L. Pinney

Person

Patents Grantslast 30 patents

Ferroelectric memory plate power reduction

Apparatuses and methods for data movement

Apparatuses and methods for partitioned parallel data movement

Cell voltage accumulation discharge

Ferroelectric memory plate power reduction

Apparatuses and methods for data movement

Apparatuses and methods for partitioned parallel data movement

Cell voltage accumulation discharge

Ferroelectric memory plate power reduction

Apparatuses and methods for data movement

Apparatuses and methods for partitioned parallel data movement

Accessing data in memory

Accessing data in memory

Apparatuses and methods for partitioned parallel data movement

Accessing data in memory

Low voltage sense amplifier and sensing method

Low voltage sense amplifier and sensing method

Dynamic well bias controlled by Vt detector

Open digit line array architecture for a memory array

Low voltage sense amplifier and sensing method

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Dual stage DRAM memory equalization

Self-test ram using external synchronous clock

Device and method for using complementary bits in a memory array

Device and method for using complementary bits in a memory array

Self-test RAM using external synchronous clock

Memory circuit having improved sense-amplifier block and method for...

Patents Applicationslast 30 patents

FERROELECTRIC MEMORY PLATE POWER REDUCTION

APPARATUSES AND METHODS FOR DATA MOVEMENT

APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT

CELL VOLTAGE ACCUMULATION DISCHARGE

FERROELECTRIC MEMORY PLATE POWER REDUCTION

FERROELECTRIC MEMORY PLATE POWER REDUCTION

CELL VOLTAGE ACCUMULATION DISCHARGE

APPARATUSES AND METHODS FOR DATA MOVEMENT

APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT

ACCESSING DATA IN MEMORY

APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT

ACCESSING DATA IN MEMORY

APPARATUSES AND METHODS FOR DATA MOVEMENT

APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT

LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD

LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD

Open digit line array architecture for a memory array

Low voltage sense amplifier and sensing method

Dynamic well bias controlled by Vt detector

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Open digit line array architecture for a memory array

Dual stage DRAM memory equalization

DUAL STAGE DRAM MEMORY EQUALIZATION

Self-test ram using external synchronous clock

Device and method for using complementary bits in a memory array

DEVICE AND METHOD FOR USING COMPLEMENTARY BITS IN A MEMORY ARRAY

Self-test ram using external synchronous clock

Equilibrate method for dynamic plate sensing memories