David P. Brunco

Person

Latham, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and structure to provide integrated long channel vertical Fi...
- Patent number 11,081,398
- Issue date Aug 3, 2021
- GLOBALEOUNDRIES U.S. INC.
- Xusheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor recess to epitaxial regions and related integrated ci...
- Patent number 10,811,422
- Issue date Oct 20, 2020
- GLOBALFOUNDRIES Inc.
- Yanping Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Late gate cut using selective conductor deposition
- Patent number 10,727,067
- Issue date Jul 28, 2020
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system having super steep retrograde well wi...
- Patent number 10,497,703
- Issue date Dec 3, 2019
- GLOBALFOUNDRIES Inc.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with fins formed by a damascene-like process
- Patent number 10,403,742
- Issue date Sep 3, 2019
- GLOBALFOUNDRIES Inc.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active gate contacts and method of fabrication thereof
- Patent number 10,347,541
- Issue date Jul 9, 2019
- GLOBALFOUNDRIES Inc.
- Jiehui Shu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with fins having independently-dimensioned...
- Patent number 10,325,811
- Issue date Jun 18, 2019
- GLOBALFOUNDRIES Inc.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system having super steep retrograde well wi...
- Patent number 10,325,913
- Issue date Jun 18, 2019
- GLOBALFOUNDRIES Inc.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for constructing FINFET devices having a super st...
- Patent number 10,062,612
- Issue date Aug 28, 2018
- GLOBALFOUNDRIES Inc.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure to provide integrated long channel vertical Fi...
- Patent number 10,014,409
- Issue date Jul 3, 2018
- GLOBALFOUNDRIES Inc.
- Xusheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-fin doping method
- Patent number 10,002,793
- Issue date Jun 19, 2018
- GLOBALFOUNDRIES Inc.
- Jiehui Shu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with self-aligned wells and multiple channe...
- Patent number 9,953,872
- Issue date Apr 24, 2018
- GLOBALFOUNDRIES Inc.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system having super steep retrograde well wi...
- Patent number 9,929,159
- Issue date Mar 27, 2018
- GLOBALFOUNDRIES Inc.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system having super steep retrograde well wi...
- Patent number 9,911,740
- Issue date Mar 6, 2018
- GLOBALFOUNDRIES Inc.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with self-aligned wells and multiple channe...
- Patent number 9,793,168
- Issue date Oct 17, 2017
- GLOBALFOUNDRIES Inc.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits including a MIMCAP device and methods of formin...
- Patent number 9,583,557
- Issue date Feb 28, 2017
- GLOBALFOUNDRIES, INC.
- Lili Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of forming strained epitaxial semiconductor material(S) abo...
- Patent number 9,490,123
- Issue date Nov 8, 2016
- GLOBALFOUNDRIES Inc.
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with self-aligned wells and multiple channe...
- Patent number 9,257,557
- Issue date Feb 9, 2016
- GLOBALFOUNDRIES Inc.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing semiconductor devices
- Patent number 9,064,702
- Issue date Jun 23, 2015
- IMEC
- David Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device with strained layer for quantum well confinement and method...
- Patent number 9,006,705
- Issue date Apr 14, 2015
- IMEC
- Geert Eneman
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for manufacturing a transistor device comprising a germanium...
- Patent number 8,828,826
- Issue date Sep 9, 2014
- IMEC
- Liesbeth Witters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming metal-germanide layers and devices obtained the...
- Patent number 8,354,344
- Issue date Jan 15, 2013
- IMEC
- David Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for producing nMOS and pMOS devices in CMOS processing
- Patent number 8,207,030
- Issue date Jun 26, 2012
- IMEC
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...
- Publication number 20200258789
- Publication date Aug 13, 2020
- GLOBALFOUNDRIES INC.
- Xusheng WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION
- Publication number 20200176258
- Publication date Jun 4, 2020
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR RECESS TO EPITAXIAL REGIONS AND RELATED INTEGRATED CI...
- Publication number 20200161315
- Publication date May 21, 2020
- GLOBALFOUNDRIES INC.
- Yanping Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...
- Publication number 20190385914
- Publication date Dec 19, 2019
- GLOBALFOUNDRIES INC.
- Xusheng WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS
- Publication number 20190273148
- Publication date Sep 5, 2019
- GLOBALFOUNDRIES INC.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH FINS HAVING INDEPENDENTLY-DIMENSIONED...
- Publication number 20190131177
- Publication date May 2, 2019
- GLOBALFOUNDRIES INC.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS
- Publication number 20190097019
- Publication date Mar 28, 2019
- GLOBALFOUNDRIES INC.
- Wei Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...
- Publication number 20180190817
- Publication date Jul 5, 2018
- GLOBALFOUNDRIES INC.
- Xusheng WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...
- Publication number 20180175037
- Publication date Jun 21, 2018
- GLOBALFOUNDRIES INC.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...
- Publication number 20180145079
- Publication date May 24, 2018
- GLOBALFOUNDRIES INC.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR CONSTRUCTING FINFET DEVICES HAVING A SUPER ST...
- Publication number 20180102291
- Publication date Apr 12, 2018
- GLOBALFOUNDRIES INC.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...
- Publication number 20180019241
- Publication date Jan 18, 2018
- GLOBALFOUNDRIES INC.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...
- Publication number 20180012805
- Publication date Jan 11, 2018
- GLOBALFOUDRIES INC.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...
- Publication number 20170250183
- Publication date Aug 31, 2017
- GLOBALFOUNDRIES INC.
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING STRAINED EPITAXIAL SEMICONDUCTOR MATERIAL(S) ABO...
- Publication number 20160118255
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES INC.
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...
- Publication number 20160111335
- Publication date Apr 21, 2016
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS INCLUDING A MIMCAP DEVICE AND METHODS OF FORMIN...
- Publication number 20160064472
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES, Inc.
- Lili Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS STRUCTURE WITH BENEFICIAL NMOS AND PMOS BAND OFFSETS
- Publication number 20160035727
- Publication date Feb 4, 2016
- GLOBALFOUNDRIES INC.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...
- Publication number 20150340500
- Publication date Nov 26, 2015
- GLOBALFOUNDRIES INC.
- David P. Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FIN...
- Publication number 20150318169
- Publication date Nov 5, 2015
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALD dielectric films with leakage-reducing impurity layers
- Publication number 20150146341
- Publication date May 28, 2015
- GLOBALFOUNDRIES, INC.
- Nobumichi Fuchigami
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
- Publication number 20140061735
- Publication date Mar 6, 2014
- IMEC
- Liesbeth Witters
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD...
- Publication number 20140054547
- Publication date Feb 27, 2014
- Geert Eneman
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES
- Publication number 20140038426
- Publication date Feb 6, 2014
- GLOBALFOUNDRIES INC.
- David Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PRODUCING NMOS AND PMOS DEVICES IN CMOS PROCESSING
- Publication number 20090272976
- Publication date Nov 5, 2009
- Interuniversitair Microelektronica Centrum vzw (IMEC)
- David Paul Brunco
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for Forming Metal-Germanide Layers and Devices Obtained The...
- Publication number 20090085167
- Publication date Apr 2, 2009
- Interuniversitair Microelektronica Centrum vzw (IMEC)
- David Brunco
- H01 - BASIC ELECTRIC ELEMENTS

David P. Brunco

Person

Patents Grantslast 30 patents

Method and structure to provide integrated long channel vertical Fi...

Semiconductor recess to epitaxial regions and related integrated ci...

Late gate cut using selective conductor deposition

Method, apparatus, and system having super steep retrograde well wi...

Field-effect transistors with fins formed by a damascene-like process

Active gate contacts and method of fabrication thereof

Field-effect transistors with fins having independently-dimensioned...

Method, apparatus, and system having super steep retrograde well wi...

Method and system for constructing FINFET devices having a super st...

Method and structure to provide integrated long channel vertical Fi...

Sub-fin doping method

Semiconductor structure with self-aligned wells and multiple channe...

Method, apparatus, and system having super steep retrograde well wi...

Method, apparatus, and system having super steep retrograde well wi...

Semiconductor structure with self-aligned wells and multiple channe...

Integrated circuits including a MIMCAP device and methods of formin...

Methods of forming strained epitaxial semiconductor material(S) abo...

Semiconductor structure with self-aligned wells and multiple channe...

Method for manufacturing semiconductor devices

Device with strained layer for quantum well confinement and method...

Method for manufacturing a transistor device comprising a germanium...

Methods for forming metal-germanide layers and devices obtained the...

Method for producing nMOS and pMOS devices in CMOS processing

Patents Applicationslast 30 patents

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...

LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION

SEMICONDUCTOR RECESS TO EPITAXIAL REGIONS AND RELATED INTEGRATED CI...

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...

FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS

FIELD-EFFECT TRANSISTORS WITH FINS HAVING INDEPENDENTLY-DIMENSIONED...

FIELD-EFFECT TRANSISTORS WITH FINS FORMED BY A DAMASCENE-LIKE PROCESS

METHOD AND STRUCTURE TO PROVIDE INTEGRATED LONG CHANNEL VERTICAL FI...

METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...

METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...

METHOD AND SYSTEM FOR CONSTRUCTING FINFET DEVICES HAVING A SUPER ST...

METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...

METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WI...

METHODS OF FORMING STRAINED EPITAXIAL SEMICONDUCTOR MATERIAL(S) ABO...

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...

INTEGRATED CIRCUITS INCLUDING A MIMCAP DEVICE AND METHODS OF FORMIN...

CMOS STRUCTURE WITH BENEFICIAL NMOS AND PMOS BAND OFFSETS

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNE...

METHODS OF FORMING EPITAXIAL SEMICONDUCTOR CLADDING MATERIAL ON FIN...

ALD dielectric films with leakage-reducing impurity layers

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

DEVICE WITH STRAINED LAYER FOR QUANTUM WELL CONFINEMENT AND METHOD...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

METHOD FOR PRODUCING NMOS AND PMOS DEVICES IN CMOS PROCESSING

Methods for Forming Metal-Germanide Layers and Devices Obtained The...