Patent Application
20150318169
1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming epitaxial semiconductor cladding material on fins of a FinFET semiconductor device.
2. Description of the Related Art
A conventional FinFET device has a three-dimensional (3D) structure that includes one or more vertically oriented fins that are formed in a semiconductor substrate.
In one illustrative process flow, after the fins 14 are formed, a gate structure (not shown) is formed over a portion of the axial length of the fins 14, a portion of the fins 14 that will become the channel region for the device 10. Next, sidewalls spacers (not shown) are formed adjacent the gate structure. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions for the device 10. The portions of the fins 14 that are in the source/drain regions may be increased in size or even merged together (a situation not shown in
As indicated in
In FinFET devices, so-called epi cladding semiconductor material, e.g., epi SiGe, may be formed in the channel region of the device, in the source/drain regions of the device or both. With reference to
The above-described process of forming this additional epi semiconductor material 24 is not without problems. First, the epi semiconductor material 24 grows at different rates on the different crystalline planes of the fin 14 and, therefore, results in the epi semiconductor material having different thicknesses at different locations around the perimeter of the fin 14. Accordingly, when such an epi semiconductor material 24 is used in the channel region of the device 10, there will be undesirable variations in the threshold voltage (Vt) of the device. Another problem that may arise when forming the epi semiconductor material 24 in the source/drain regions of the device is, for example, despite best efforts to tightly control the process, the epi semiconductor material 24 may be grown to such an extent that the epi semiconductor material 24 is formed in areas where it should not be located and/or is formed in such quantities that the epi semiconductor material 24 on adjacent fins 14 may undesirably merge with one another. This is especially true in closely-packed device areas such as SRAM areas. Obviously, such unanticipated merging of the epi semiconductor material 24 on the fins 14 can cause the device 10 to function at a lesser level than that anticipated by the design process. In a worst-case scenario, the epi material 24 that is formed on, for example, an NMOS device may inadvertently merge with the epi semiconductor material 24 formed on a fin of a PMOS device (or vice-versa). In such a situation, an electrical short may be created and the device 10 may have to be scrapped.
Efforts have been made to reduce the non-uniform growth of the diamond-shaped epi semiconductor material 24 discussed above. One technique that has been tried to grow epi semiconductor material in a more conformal manner involves orienting the fins 14 in a particular crystallographic orientation. For example,
What is needed is a method of forming epi semiconductor material in a very conformal manner such that it has more uniform thickness at all locations around the fin. Growth of such a uniform material would perhaps allow the more conformal and uniform-thickness epi material to be used in the channel region of a FinFET device and reduce or eliminate the problems associated with forming the diamond-shaped epi semiconductor material 24 in the source/drain regions of the device. The present disclosure is directed to various methods of forming epitaxial semiconductor cladding material on fins of a FinFET semiconductor device that may solve or reduce one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming epitaxial semiconductor cladding material on fins of a FinFET semiconductor device. One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.
Another illustrative embodiment includes, among other things, forming a fin in a (100) silicon substrate, wherein a long axis of the fin is oriented in a <110> crystallographic direction of the substrate, and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and hydrogen to form a silicon germanium (Si(1-x)Gex) epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.
Yet another illustrative embodiment includes, among other things, forming a fin in a semiconductor substrate and performing a sequential epitaxial deposition process to form an epi semiconductor material around the fin, wherein the sequential deposition process comprises performing at least one first deposition process using one of silane (SiH4) or dichlorosilane (SiH2Cl2) in combination with germane (GeH4) and a carrier gas to form a first portion of the epi semiconductor material and, after completing the first deposition process, performing at least one second deposition process using the other of silane (SiH4) or dichlorosilane (SiH2Cl2) in combination with germane (GeH4) and a carrier gas to form a second portion of the epi semiconductor material on the first portion of the epi semiconductor material.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming epitaxial semiconductor cladding material on fins of a FinFET semiconductor device. The cladding material may be formed for the channel region of the device, the source/drain regions for the device, or both. The method disclosed herein may be employed in manufacturing either an N-type device or a P-type device, and the gate structure of such devices may be formed using either so-called “gate-first” or “replacement gate” (“gate-last”) techniques. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
The inventors have discovered that, quite unexpectedly, in lieu of using only silane or only DCS as the source of silicon when forming a silicon germanium (Si(1-x)Gex) epitaxial cladding material on a silicon fin (as depicted in
At the point of fabrication depicted in
As indicated in
As used herein and in the claims, the term “fin” or “fins” should be understood to mean a three-dimensional structure that is comprised, in whole or part, of the material of the substrate. That is, in one example, the fins 114 may have a substantially uniform construction, i.e., they may be formed entirely of the material of the substrate 112, e.g., silicon. Thereafter, epi semiconductor material may be formed on exposed surfaces of the fins 114 using the methods disclosed herein. Additionally, in one embodiment, the silicon germanium (Si(1-x)Gex) epitaxial cladding material disclosed herein may be formed around the entire axial length 114L of the fins 114 prior to the formation of any type of gate structure. In another embodiment, the methods disclosed herein may be used to form epi semiconductor material in the source/drain regions of the device, irrespective of whether epi semiconductor material is formed in the channel region of the device 100. In yet another embodiment, a condensation process may be performed to form fins comprised of homogenous silicon germanium (Si(1-x)Gex) material.
One illustrative process flow that may be employed to form the device 100 on a non-rotated (100) substrate 112 will now be described with reference to the following drawings. Of course, other process flows may be used to form the fins 114 of the device 100 disclosed herein. Thus, the methods and devices disclosed herein should not be considered to be limited to the illustrative process flow described herein.
The parameters of the epi process may vary depending upon the particular application. For example, in one illustrative embodiment where the epitaxial semiconductor cladding material 130 is silicon germanium (Si(1-x)Gex) that is formed on a silicon fin 114, the epi process may be performed under the following conditions:
Pressure=10-200 Torr, with about 50 Torr being one preferred example;
Temperature=350-750° C., with about 405° C. being one preferred example;
Carrier Gas=Hydrogen at a flow rate between 3,000-50,000 sccm, with about 20,000 sccm being one preferred example;
DCS=5-100 sccm, with about 20 sccm being one preferred example;
Silane=5-100 sccm, with about 40 sccm being one preferred example; and
Germane=50-500 sccm (10% diluted in H2), with about 150 sccm being one preferred example.
In general, the inventors have discovered that forming the more uniform epitaxial semiconductor cladding material 130 disclosed herein may be achieved when the epi deposition process is performed when the amount of DCS is set to be about 10-90% of the total combined flow rate of both DCS and silane. In the preferred example mentioned above, the DCS is 33.3% (20 sccm) of the combined flow rate of both the DCS and the silane (60 sccm). The inventors have discovered that a high germane versus silane and DCS ratio (meaning higher germanium content SiGe materials) may be preferred for more uniform epitaxial cladding. In the preferred example, a germane versus silane and DCS ratio 150/60 is used to form Si0.25Ge0.75 material.
In another illustrative embodiment, a sequential deposition process may be performed using silane and DCS in any desired order. For example, in one embodiment, the epi semiconductor material 130 may be formed by performing a first chemical vapor deposition process using silane, germane and a carrier gas to form a first portion of the epitaxial semiconductor cladding material 130. Thereafter, a second chemical vapor deposition process may be performed using DCS, germane and a carrier gas to form a second portion of the epitaxial semiconductor cladding material 130 on the previously-formed first portion of epitaxial semiconductor cladding material 130. Of course, if desired, the DCS-based deposition sequence could be performed prior to the silane-based deposition sequence. The sequential deposition process may be repeated as often as needed to develop the desired thickness of the epi semiconductor material 130. Importantly, this sequential deposition process may be performed in a single process chamber and without breaking the processing ambient and exposing the device to ambient room conditions. The gas flow rates and process conditions for this sequential deposition embodiment are the same as those noted above, with the DCS or silane (as the case may be) omitted.
As noted above, it is believed that by using the combination of both silane and DCS as the source of silicon in the epi deposition process, the resulting configuration of the silicon germanium (Si(1-x)Gex) epitaxial cladding material 130 reflects an unexpected combination of the profiles that were typically achieved when using only silane or only DCS as the source of silicon in the epi deposition process that included germane. Prior to the discovery of the present invention, process engineers knew that a source of silicon was required to form epi silicon germanium material, and silane and DCS were simply viewed as being substantially interchangeable sources of silicon. Prior to the present discovery, there was no perceived benefit or motivation to use multiple sources of silicon in the epi formation process.
In one embodiment, the epitaxial semiconductor cladding material 130 is formed along the entire axial length 114L of the fin 114 and at least a portion of the cladding material 130 will be part of the channel region of the device 100. In one embodiment, when formed in the channel region of the device 100, the epitaxial semiconductor cladding material 130 may have a thickness that falls within the range of about 2-10 nm. After the formation of the epitaxial semiconductor cladding material 130, traditional processing operations may be performed to complete the fabrication of the device 100. For example, as shown in
In another embodiment, the methods disclosed herein may be employed to form the epitaxial semiconductor material 130 in both the channel region of the device as well as in the source/drain regions of the device. The epi material 130 in the source/drain regions may be doped with the appropriate dopant materials in situ, e.g., P-type dopants for a P-type device or N-type dopants for an N-type device. In this embodiment, the epitaxial semiconductor cladding material 130 may initially be formed so as to cover the entire axial length 114L of the fins 114. Thereafter, the above-described gate structure 150 may be formed over a portion of the fins (the channel region) and sidewall spacers may be formed adjacent the gate structure. At that point, a cleaning process may be performed on the source/drain regions of the device in advance of forming epi material in the source/drain regions. This cleaning process may or may not remove all of the epitaxial semiconductor cladding material 130 that was initially formed on the fins 114. Thereafter, the methods disclosed herein may be performed to form epitaxial semiconductor cladding material 130 in the source/drain regions of the device 100. In this illustrative embodiment, the epitaxial semiconductor cladding material 130 in the channel region of the device 100 may have a thickness of about 2-10 nm, while the epitaxial semiconductor cladding material 130 formed in the source/drain regions may be significantly thicker, e.g., 5-60 nm. By virtue of the highly conformal nature of the epitaxial semiconductor cladding material 130 formed as disclosed herein, a highly desirable and relatively thin layer of epitaxial semiconductor cladding material 130 may be formed in the channel region of the device, and a significant amount of epitaxial semiconductor cladding material 130 may be formed in the source/drain regions while reducing the chances of undesirable fin merger occurring.
In yet another embodiment, the epitaxial semiconductor cladding material 130 disclosed herein may be formed only in the source/drain regions of the device 100, i.e., after the above-described gate structure 150 is formed and associated sidewall spacers are formed adjacent the gate structure. In such a case, the epitaxial semiconductor cladding material 130 would not be positioned in the channel region of the device 100. In this embodiment, the gate structure 150 is formed so as to cover the bare fin 114 in the channel region of the device and the sidewall spacers are then formed adjacent the gate structure. At that point, a cleaning process may be performed on the source/drain regions of the device. Thereafter, the methods disclosed herein may be performed to form epitaxial semiconductor cladding material 130 in the source/drain regions of the device 100. As noted above, by virtue of the highly conformal nature of the epitaxial semiconductor cladding material 130 formed as disclosed herein, a significant amount of epitaxial semiconductor cladding material 130 may be formed in the source/drain regions while reducing the chances of undesirable fin merger occurring.
Additionally, a fin condensation thermal anneal process may be performed on the device after the formation of the epitaxial semiconductor cladding material 130 so as to further increase the conformal nature of the epitaxial semiconductor cladding material 130. In one illustrative embodiment, the fin condensation thermal anneal process may be performed at a temperature that falls within the range of about 500-800° C. using an RTA furnace, a laser anneal process or a traditional furnace, depending upon the particular application. The fin condensation thermal anneal process must be performed in an oxidizing processing ambient. During the fin condensation thermal anneal process, some of the outer portions of the overall fin structure is oxidized, thereby producing a thinner, more condensed fin.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
