David R. Stiles

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for debugging an integrated circuit
- Patent number 6,499,123
- Issue date Dec 24, 2002
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction device with two levels of branch prediction cache
- Patent number 6,425,075
- Issue date Jul 23, 2002
- Advanced Micro Devices, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for executing string instructions
- Patent number 6,212,629
- Issue date Apr 3, 2001
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Branch prediction device with two levels of branch prediction cache
- Patent number 6,067,616
- Issue date May 23, 2000
- Advanced Micro Devices, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple level cache control system with address and data pipelines
- Patent number 6,021,471
- Issue date Feb 1, 2000
- Advanced Micro Devices, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Set-associative cache memory utilizing a single bank of physical me...
- Patent number 5,905,997
- Issue date May 18, 1999
- AMD Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer processor with distributed pipeline control that allows fu...
- Patent number 5,881,265
- Issue date Mar 9, 1999
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for superscalar instruction pre-decoding using cached ins...
- Patent number 5,832,259
- Issue date Nov 3, 1998
- Advanced Micro Devices, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for concurrent access to multiple physical caches
- Patent number 5,826,052
- Issue date Oct 20, 1998
- Advanced Micro Devices, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semi-autonomous RISC pipelines for overlapped execution of RISC-lik...
- Patent number 5,781,753
- Issue date Jul 14, 1998
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semi-Autonomous RISC pipelines for overlapped execution of RISC-lik...
- Patent number 5,768,575
- Issue date Jun 16, 1998
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing floating point addition
- Patent number 5,764,556
- Issue date Jun 9, 1998
- Advanced Micro Devices, Inc.
- David Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system for dynamically altering single cache memory li...
- Patent number 5,748,932
- Issue date May 5, 1998
- Advanced Micro Devices, Inc.
- Korbin S. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer processor with distributed pipeline control that allows fu...
- Patent number 5,682,492
- Issue date Oct 28, 1997
- Advanced Micro Devices, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for store-into-instruction-stream detection an...
- Patent number 5,649,137
- Issue date Jul 15, 1997
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level branch prediction cache
- Patent number 5,515,518
- Issue date May 7, 1996
- NexGen, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for superscalar instruction predecoding using cached inst...
- Patent number 5,513,330
- Issue date Apr 30, 1996
- NexGen, Inc.
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method an apparatus for store-into-instruction-stream detection and...
- Patent number 5,511,175
- Issue date Apr 23, 1996
- NexGen, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer processor with distributed pipeline control that allows fu...
- Patent number 5,442,757
- Issue date Aug 15, 1995
- NexGen, Inc.
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level branch prediction cache
- Patent number 5,327,547
- Issue date Jul 5, 1994
- NexGen Microsystems
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system for dynamically altering single cache memory li...
- Patent number 5,230,068
- Issue date Jul 20, 1993
- NexGen Microsystems
- Korbin S. Van Dyke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for store-into-instruction-stream detection an...
- Patent number 5,226,130
- Issue date Jul 6, 1993
- NexGen Microsystems
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having plurality of functional units for orderly retiring...
- Patent number 5,226,126
- Issue date Jul 6, 1993
- Nexgen Microsystems
- Harold L. McFarland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level branch prediction cache
- Patent number 5,163,140
- Issue date Nov 10, 1992
- Nexgen Microsystems
- David R. Stiles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated single structure branch prediction cache
- Patent number 5,093,778
- Issue date Mar 3, 1992
- Nexgen Microsystems
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING

David R. Stiles

Person

Patents Grantslast 30 patents

Method and apparatus for debugging an integrated circuit

Branch prediction device with two levels of branch prediction cache

Method and apparatus for executing string instructions

Branch prediction device with two levels of branch prediction cache

Multiple level cache control system with address and data pipelines

Set-associative cache memory utilizing a single bank of physical me...

Computer processor with distributed pipeline control that allows fu...

Apparatus for superscalar instruction pre-decoding using cached ins...

Method and apparatus for concurrent access to multiple physical caches

Semi-autonomous RISC pipelines for overlapped execution of RISC-lik...

Semi-Autonomous RISC pipelines for overlapped execution of RISC-lik...

Method and apparatus for performing floating point addition

Cache memory system for dynamically altering single cache memory li...

Computer processor with distributed pipeline control that allows fu...

Method and apparatus for store-into-instruction-stream detection an...

Two-level branch prediction cache

Apparatus for superscalar instruction predecoding using cached inst...

Method an apparatus for store-into-instruction-stream detection and...

Computer processor with distributed pipeline control that allows fu...

Two-level branch prediction cache

Cache memory system for dynamically altering single cache memory li...

Method and apparatus for store-into-instruction-stream detection an...

Processor having plurality of functional units for orderly retiring...

Two-level branch prediction cache

Integrated single structure branch prediction cache